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cnss2: Add code to address boot timer debug corner case

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To handle corner case where mhi power on success and the boot
debug timer handler execution(i.e dumping register) runs parellel.
Even-though the timer is deleted as soon as mhi is powered on,
as this handler is still running it is armed again. Use the
del_timer_sync api which makes sure the timer is not queued and
the handler is not running upon its exit.

Change-Id: Ie428f3e8af8870018dfed99a5472afca14116bb3
This commit is contained in:
Mohammed Siddiq
2022-05-12 14:18:32 +05:30
parent 8ebc3d7e4f
commit 04bdb792b7
1 changed files with 1 additions and 1 deletions
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2
cnss2/pci.c
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@@ -2184,7 +2184,7 @@ int cnss_pci_start_mhi(struct cnss_pci_data *pci_priv)
jiffies + msecs_to_jiffies(BOOT_DEBUG_TIMEOUT_MS));
ret = cnss_pci_set_mhi_state(pci_priv, CNSS_MHI_POWER_ON);
del_timer(&pci_priv->boot_debug_timer);
del_timer_sync(&pci_priv->boot_debug_timer);
if (ret == 0)
cnss_wlan_adsp_pc_enable(pci_priv, false);