video: driver: Add changes to enable AV1 Decoder

Add definitions, controls and codec-specific handling
to enable AV1 Decoder.

Change-Id: Ica2f4e298e43aa713188d3374f8705688d0ed912
Signed-off-by: Mihir Ganu <quic_mganu@quicinc.com>
Bu işleme şunda yer alıyor:
Mihir Ganu
2021-12-03 13:27:39 -08:00
ebeveyn 1068661f6d
işleme 04304a466f
9 değiştirilmiş dosya ile 227 ekleme ve 20 silme

Dosyayı Görüntüle

@@ -48,13 +48,14 @@
#define H264 MSM_VIDC_H264
#define HEVC MSM_VIDC_HEVC
#define VP9 MSM_VIDC_VP9
#define AV1 MSM_VIDC_AV1
#define HEIC MSM_VIDC_HEIC
#define CODECS_ALL (H264 | HEVC | VP9 | HEIC)
#define CODECS_ALL (H264 | HEVC | VP9 | HEIC | AV1)
static struct msm_platform_core_capability core_data_kalama[] = {
/* {type, value} */
{ENC_CODECS, H264|HEVC|HEIC},
{DEC_CODECS, H264|HEVC|VP9|HEIC},
{DEC_CODECS, H264|HEVC|VP9|AV1|HEIC},
{MAX_SESSION_COUNT, 16},
{MAX_NUM_720P_SESSIONS, 16},
{MAX_NUM_1080P_SESSIONS, 8},
@@ -185,6 +186,13 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
MSM_VIDC_FMT_P010 | MSM_VIDC_FMT_TP10C,
MSM_VIDC_FMT_NV12C},
{PIX_FMTS, DEC, AV1,
MSM_VIDC_FMT_NV12,
MSM_VIDC_FMT_TP10C,
MSM_VIDC_FMT_NV12 | MSM_VIDC_FMT_NV21 | MSM_VIDC_FMT_NV12C |
MSM_VIDC_FMT_P010 | MSM_VIDC_FMT_TP10C,
MSM_VIDC_FMT_NV12C},
{MIN_BUFFERS_INPUT, ENC|DEC, CODECS_ALL, 0, 64, 1, 4,
V4L2_CID_MIN_BUFFERS_FOR_OUTPUT},
{MIN_BUFFERS_OUTPUT, ENC|DEC, CODECS_ALL,
@@ -202,10 +210,10 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
{LOSSLESS_MBPF, ENC, H264|HEVC, 64, 36864, 1, 36864},
/* Batch Mode Decode */
/* TODO: update with new values based on updated voltage corner */
{BATCH_MBPF, DEC, H264|HEVC|VP9, 64, 34816, 1, 34816},
{BATCH_MBPF, DEC, H264|HEVC|VP9|AV1, 64, 34816, 1, 34816},
/* (4096 * 2304) / 256 */
{BATCH_FPS, DEC, H264|HEVC|VP9, 1, 120, 1, 120},
{SECURE_MBPF, ENC|DEC, H264|HEVC|VP9, 64, 36864, 1, 36864},
{BATCH_FPS, DEC, H264|HEVC|VP9|AV1, 1, 120, 1, 120},
{SECURE_MBPF, ENC|DEC, H264|HEVC|VP9|AV1, 64, 36864, 1, 36864},
/* ((1920 * 1088) / 256) * 480 fps */
{MBPS, ENC, CODECS_ALL, 64, 3916800, 1, 3916800},
/* ((1920 * 1088) / 256) * 960 fps */
@@ -252,7 +260,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
{MB_CYCLES_FW, ENC|DEC, CODECS_ALL, 326389, 326389, 1, 326389},
{MB_CYCLES_FW_VPP, ENC|DEC, CODECS_ALL, 44156, 44156, 1, 44156},
{SECURE_MODE, ENC|DEC, H264|HEVC|VP9,
{SECURE_MODE, ENC|DEC, H264|HEVC|VP9|AV1,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
V4L2_CID_MPEG_VIDC_SECURE,
@@ -518,7 +526,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
{STAGE},
msm_vidc_adjust_lowlatency_mode, NULL},
{LOWLATENCY_MODE, DEC, H264|HEVC|VP9,
{LOWLATENCY_MODE, DEC, H264|HEVC|VP9|AV1,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
V4L2_CID_MPEG_VIDC_LOWLATENCY_REQUEST,
@@ -967,7 +975,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
{0},
msm_vidc_adjust_entropy_mode, msm_vidc_set_u32},
{ENTROPY_MODE, DEC, H264|HEVC|VP9,
{ENTROPY_MODE, DEC, H264|HEVC|VP9|AV1,
V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC,
V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CABAC,
BIT(V4L2_MPEG_VIDEO_H264_ENTROPY_MODE_CAVLC) |
@@ -1060,6 +1068,60 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
{0},
NULL, msm_vidc_set_u32_enum},
{PROFILE, DEC, AV1,
V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
BIT(V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN),
V4L2_MPEG_VIDEO_AV1_PROFILE_MAIN,
V4L2_CID_MPEG_VIDEO_AV1_PROFILE,
HFI_PROP_PROFILE,
CAP_FLAG_ROOT | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
{0},
{0},
NULL, msm_vidc_set_u32_enum},
{LEVEL, DEC, AV1,
V4L2_MPEG_VIDEO_AV1_LEVEL_2_0,
V4L2_MPEG_VIDEO_AV1_LEVEL_6_1,
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_0) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_1) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_2) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_2_3) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_0) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_1) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_2) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_3_3) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_0) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_1) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_2) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_4_3) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_0) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_1) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_2) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_5_3) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_0) |
BIT(V4L2_MPEG_VIDEO_AV1_LEVEL_6_1),
V4L2_MPEG_VIDEO_AV1_LEVEL_6_1,
V4L2_CID_MPEG_VIDEO_AV1_LEVEL,
HFI_PROP_LEVEL,
CAP_FLAG_ROOT | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
{0},
{0},
NULL, msm_vidc_set_u32_enum},
{AV1_TIER, DEC, AV1,
V4L2_MPEG_VIDEO_AV1_TIER_MAIN,
V4L2_MPEG_VIDEO_AV1_TIER_HIGH,
BIT(V4L2_MPEG_VIDEO_AV1_TIER_MAIN) |
BIT(V4L2_MPEG_VIDEO_AV1_TIER_HIGH),
V4L2_MPEG_VIDEO_AV1_TIER_HIGH,
V4L2_CID_MPEG_VIDEO_AV1_TIER,
HFI_PROP_TIER,
CAP_FLAG_ROOT | CAP_FLAG_OUTPUT_PORT | CAP_FLAG_MENU,
{0},
{0},
NULL, msm_vidc_set_u32_enum},
{LEVEL, DEC, H264,
V4L2_MPEG_VIDEO_H264_LEVEL_1_0,
V4L2_MPEG_VIDEO_H264_LEVEL_6_2,
@@ -1276,14 +1338,14 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
msm_vidc_adjust_chroma_qp_index_offset,
msm_vidc_set_chroma_qp_index_offset},
{DISPLAY_DELAY_ENABLE, DEC, H264|HEVC|VP9,
{DISPLAY_DELAY_ENABLE, DEC, H264|HEVC|VP9|AV1,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY_ENABLE,
HFI_PROP_DECODE_ORDER_OUTPUT,
CAP_FLAG_ROOT | CAP_FLAG_INPUT_PORT},
{DISPLAY_DELAY, DEC, H264|HEVC|VP9,
{DISPLAY_DELAY, DEC, H264|HEVC|VP9|AV1,
0, 1, 1, 0,
V4L2_CID_MPEG_VIDEO_DEC_DISPLAY_DELAY,
HFI_PROP_DECODE_ORDER_OUTPUT,
@@ -1348,7 +1410,7 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
0,
HFI_PROP_LUMA_CHROMA_BIT_DEPTH},
{CODEC_CONFIG, DEC, H264|HEVC|HEIC, 0, 1, 1, 0,
{CODEC_CONFIG, DEC, H264|HEVC|HEIC|AV1, 0, 1, 1, 0,
V4L2_CID_MPEG_VIDC_CODEC_CONFIG, 0,
CAP_FLAG_DYNAMIC_ALLOWED},
@@ -1405,6 +1467,18 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
{0}, {0},
NULL, NULL},
{FILM_GRAIN, DEC, AV1,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
0,
HFI_PROP_AV1_FILM_GRAIN_PRESENT},
{SUPER_BLOCK, DEC, AV1,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
0,
HFI_PROP_AV1_SUPER_BLOCK_ENABLED},
{META_LTR_MARK_USE, ENC, H264|HEVC,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
@@ -1453,19 +1527,19 @@ static struct msm_platform_inst_capability instance_data_kalama[] = {
V4L2_CID_MPEG_VIDC_METADATA_HISTOGRAM_INFO,
HFI_PROP_HISTOGRAM_INFO},
{META_SEI_MASTERING_DISP, DEC|ENC, HEVC|HEIC,
{META_SEI_MASTERING_DISP, DEC|ENC, HEVC|HEIC|AV1,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
V4L2_CID_MPEG_VIDC_METADATA_SEI_MASTERING_DISPLAY_COLOUR,
HFI_PROP_SEI_MASTERING_DISPLAY_COLOUR},
{META_SEI_CLL, DEC|ENC, HEVC|HEIC,
{META_SEI_CLL, DEC|ENC, HEVC|HEIC|AV1,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
V4L2_CID_MPEG_VIDC_METADATA_SEI_CONTENT_LIGHT_LEVEL,
HFI_PROP_SEI_CONTENT_LIGHT_LEVEL},
{META_HDR10PLUS, DEC | ENC, HEVC|HEIC,
{META_HDR10PLUS, DEC | ENC, HEVC|HEIC|AV1,
V4L2_MPEG_MSM_VIDC_DISABLE, V4L2_MPEG_MSM_VIDC_ENABLE,
1, V4L2_MPEG_MSM_VIDC_DISABLE,
V4L2_CID_MPEG_VIDC_METADATA_HDR10PLUS,