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@@ -1,6 +1,6 @@
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// SPDX-License-Identifier: GPL-2.0-only
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/*
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- * Copyright (c) 2021 Qualcomm Innovation Center, Inc. All rights reserved.
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+ * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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/*
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@@ -236,9 +236,9 @@ static int dp_vco_pll_init_db_4nm(struct dp_pll_db *pdb,
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pdb->lock_cmp2_mode0 = 0x0e;
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pdb->phy_vco_div = 0x1;
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pdb->lock_cmp_en = 0x08;
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- pdb->ssc_step_size1_mode0 = 0x13;
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+ pdb->ssc_step_size1_mode0 = 0x45;
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pdb->ssc_step_size2_mode0 = 0x06;
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- pdb->ssc_per1 = 0x40;
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+ pdb->ssc_per1 = 0x36;
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pdb->cmp_code1_mode0 = 0xE2;
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pdb->cmp_code2_mode0 = 0x18;
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break;
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@@ -252,9 +252,9 @@ static int dp_vco_pll_init_db_4nm(struct dp_pll_db *pdb,
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pdb->lock_cmp2_mode0 = 0x1c;
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pdb->phy_vco_div = 0x2;
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pdb->lock_cmp_en = 0x08;
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- pdb->ssc_step_size1_mode0 = 0x1a;
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+ pdb->ssc_step_size1_mode0 = 0x5C;
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pdb->ssc_step_size2_mode0 = 0x08;
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- pdb->ssc_per1 = 0x40;
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+ pdb->ssc_per1 = 0x36;
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pdb->cmp_code1_mode0 = 0x2E;
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pdb->cmp_code2_mode0 = 0x21;
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break;
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@@ -268,9 +268,9 @@ static int dp_vco_pll_init_db_4nm(struct dp_pll_db *pdb,
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pdb->lock_cmp2_mode0 = 0x2a;
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pdb->phy_vco_div = 0x0;
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pdb->lock_cmp_en = 0x08;
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- pdb->ssc_step_size1_mode0 = 0x13;
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+ pdb->ssc_step_size1_mode0 = 0x45;
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pdb->ssc_step_size2_mode0 = 0x06;
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- pdb->ssc_per1 = 0x40;
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+ pdb->ssc_per1 = 0x36;
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pdb->cmp_code1_mode0 = 0xE2;
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pdb->cmp_code2_mode0 = 0x18;
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break;
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@@ -354,9 +354,9 @@ static int dp_config_vco_rate_4nm(struct dp_pll *pll,
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if (pll->bonding_en)
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dp_pll_write(dp_pll, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1f);
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else
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- dp_pll_write(dp_pll, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x1D);
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+ dp_pll_write(dp_pll, QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x17);
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- dp_pll_write(dp_pll, QSERDES_COM_CORE_CLK_EN, 0x1f);
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+ dp_pll_write(dp_pll, QSERDES_COM_CORE_CLK_EN, 0x0f);
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dp_pll_write(dp_pll, QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0, pdb->cmp_code1_mode0);
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dp_pll_write(dp_pll, QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0, pdb->cmp_code2_mode0);
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/* Make sure the PHY register writes are done */
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@@ -393,8 +393,8 @@ static int dp_config_vco_rate_4nm(struct dp_pll *pll,
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dp_pll_write(dp_ln_tx0, DP_TRAN_DRVR_EMP_EN, 0xf);
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dp_pll_write(dp_ln_tx0, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
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dp_pll_write(dp_ln_tx0, DP_TX_INTERFACE_MODE, 0x00);
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- dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_TX, 0x0A);
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- dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
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+ dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_TX, 0x0C);
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+ dp_pll_write(dp_ln_tx0, TXn_RES_CODE_LANE_OFFSET_RX, 0x0C);
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dp_pll_write(dp_ln_tx0, TXn_TX_BAND, 0x04);
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/* Make sure the PLL register writes are done */
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wmb();
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@@ -409,8 +409,8 @@ static int dp_config_vco_rate_4nm(struct dp_pll *pll,
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dp_pll_write(dp_ln_tx1, DP_TRAN_DRVR_EMP_EN, 0xf);
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dp_pll_write(dp_ln_tx1, TXn_PARRATE_REC_DETECT_IDLE_EN, 0x00);
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dp_pll_write(dp_ln_tx1, DP_TX_INTERFACE_MODE, 0x00);
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- dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_TX, 0x0A);
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- dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_RX, 0x11);
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+ dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_TX, 0x0C);
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+ dp_pll_write(dp_ln_tx1, TXn_RES_CODE_LANE_OFFSET_RX, 0x0C);
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dp_pll_write(dp_ln_tx1, TXn_TX_BAND, 0x04);
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/* Make sure the PHY register writes are done */
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wmb();
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