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soc: Fix PCM Port Config and CLK_CTRL Writes

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Simplify register write logic for PCM ports due to multi-ee changes.
Update SWRM_MCP_CTRL to SWRM_CLK_CTRL(ee).

Change-Id: I36e78f3f2abdb65925b141d5192adf618697d674
Signed-off-by: Matthew Rice <quic_mrice@quicinc.com>
This commit is contained in:
Matthew Rice
2021-12-01 14:48:00 -08:00
committed by Gerrit - the friendly Code Review server
parent e898bc09d6
commit 0209346e14
2 changed files with 23 additions and 34 deletions
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44
soc/swr-mstr-ctrl.c
View File

@@ -774,25 +774,13 @@ static int swrm_pcm_port_config(struct swr_mstr_ctrl *swrm, u8 port_num,
return -EINVAL; return -EINVAL;
} }
switch (stream_type) { if (stream_type == SWR_PDM)
case SWR_PCM:
reg_addr = ((dir) ? SWRM_DIN_DP_PCM_PORT_CTRL(port_num) : \
SWRM_DOUT_DP_PCM_PORT_CTRL(port_num));
swr_master_write(swrm, reg_addr, enable);
reg_val = 1;
break;
case SWR_PDM_32:
break;
case SWR_PDM:
default:
return 0; return 0;
}
if (enable) {
reg_addr = ((dir) ? SWRM_DIN_DP_PCM_PORT_CTRL(port_num) : \ reg_addr = ((dir) ? SWRM_DIN_DP_PCM_PORT_CTRL(port_num) : \
SWRM_DOUT_DP_PCM_PORT_CTRL(port_num)); SWRM_DOUT_DP_PCM_PORT_CTRL(port_num));
/* Ungate Clock Bit */ reg_val = enable ? 0x3 : 0x0;
swr_master_write(swrm, reg_addr, reg_val |= 0x02); swr_master_write(swrm, reg_addr, reg_val);
}
return 0; return 0;
} }
@@ -926,7 +914,9 @@ retry_read:
usleep_range(500, 505); usleep_range(500, 505);
if (retry_attempt == (MAX_FIFO_RD_FAIL_RETRY - 1)) { if (retry_attempt == (MAX_FIFO_RD_FAIL_RETRY - 1)) {
swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1); swr_master_write(swrm, SWRM_CMD_FIFO_CMD, 0x1);
swr_master_write(swrm, SWRM_CMD_FIFO_RD_CMD(swrm->ee_val), val); swr_master_write(swrm,
SWRM_CMD_FIFO_RD_CMD(swrm->ee_val),
val);
} }
retry_attempt++; retry_attempt++;
goto retry_read; goto retry_read;
@@ -2196,7 +2186,8 @@ handle_irq:
__func__); __func__);
swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION; swrm->intr_mask &= ~SWRM_INTERRUPT_STATUS_DOUT_PORT_COLLISION;
swr_master_write(swrm, swr_master_write(swrm,
SWRM_INTERRUPT_EN(swrm->ee_val), swrm->intr_mask); SWRM_INTERRUPT_EN(swrm->ee_val),
swrm->intr_mask);
break; break;
case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH: case SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH:
dev_dbg(swrm->dev, dev_dbg(swrm->dev,
@@ -2205,7 +2196,8 @@ handle_irq:
swrm->intr_mask &= swrm->intr_mask &=
~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH; ~SWRM_INTERRUPT_STATUS_READ_EN_RD_VALID_MISMATCH;
swr_master_write(swrm, swr_master_write(swrm,
SWRM_INTERRUPT_EN(swrm->ee_val), swrm->intr_mask); SWRM_INTERRUPT_EN(swrm->ee_val),
swrm->intr_mask);
break; break;
case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED: case SWRM_INTERRUPT_STATUS_SPECIAL_CMD_ID_FINISHED:
complete(&swrm->broadcast); complete(&swrm->broadcast);
@@ -2573,7 +2565,7 @@ static int swrm_master_init(struct swr_mstr_ctrl *swrm)
reg[len] = SWRM_LINK_MANAGER_EE; reg[len] = SWRM_LINK_MANAGER_EE;
value[len++] = swrm->ee_val; value[len++] = swrm->ee_val;
} }
reg[len] = SWRM_MCP_BUS_CTRL; reg[len] = SWRM_CLK_CTRL(swrm->ee_val);
if (swrm->version < SWRM_VERSION_1_7) if (swrm->version < SWRM_VERSION_1_7)
value[len++] = 0x2; value[len++] = 0x2;
else else
@@ -3145,7 +3137,8 @@ static int swrm_clk_pause(struct swr_mstr_ctrl *swrm)
u32 val; u32 val;
dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state); dev_dbg(swrm->dev, "%s: state: %d\n", __func__, swrm->state);
swr_master_write(swrm, SWRM_INTERRUPT_EN(swrm->ee_val), SWRM_INTERRUPT_STATUS_MASK); swr_master_write(swrm, SWRM_INTERRUPT_EN(swrm->ee_val),
SWRM_INTERRUPT_STATUS_MASK);
val = swr_master_read(swrm, SWRM_MCP_CFG); val = swr_master_read(swrm, SWRM_MCP_CFG);
val |= 0x02; val |= 0x02;
swr_master_write(swrm, SWRM_MCP_CFG, val); swr_master_write(swrm, SWRM_MCP_CFG, val);
@@ -3244,7 +3237,8 @@ static int swrm_runtime_resume(struct device *dev)
} }
swr_master_write(swrm, SWRM_COMP_SW_RESET, 0x01); swr_master_write(swrm, SWRM_COMP_SW_RESET, 0x01);
swr_master_write(swrm, SWRM_COMP_SW_RESET, 0x01); swr_master_write(swrm, SWRM_COMP_SW_RESET, 0x01);
swr_master_write(swrm, SWRM_MCP_BUS_CTRL, 0x01); swr_master_write(swrm,
SWRM_CLK_CTRL(swrm->ee_val), 0x01);
swrm_master_init(swrm); swrm_master_init(swrm);
/* wait for hw enumeration to complete */ /* wait for hw enumeration to complete */
usleep_range(100, 105); usleep_range(100, 105);
@@ -3269,9 +3263,11 @@ static int swrm_runtime_resume(struct device *dev)
else else
val = 0x2 << swrm->ee_val; val = 0x2 << swrm->ee_val;
/*wake up from clock stop*/ /*wake up from clock stop*/
swr_master_write(swrm, SWRM_MCP_BUS_CTRL, val); swr_master_write(swrm,
SWRM_CLK_CTRL(swrm->ee_val), val);
/* clear and enable bus clash interrupt */ /* clear and enable bus clash interrupt */
swr_master_write(swrm, SWRM_INTERRUPT_CLEAR(swrm->ee_val), 0x08); swr_master_write(swrm,
SWRM_INTERRUPT_CLEAR(swrm->ee_val), 0x08);
swrm->intr_mask |= 0x08; swrm->intr_mask |= 0x08;
swr_master_write(swrm, SWRM_INTERRUPT_EN(swrm->ee_val), swr_master_write(swrm, SWRM_INTERRUPT_EN(swrm->ee_val),
swrm->intr_mask); swrm->intr_mask);

9
soc/swr-mstr-ctrl.h
View File

@@ -15,7 +15,7 @@
#include <linux/debugfs.h> #include <linux/debugfs.h>
#include <linux/uaccess.h> #include <linux/uaccess.h>
#define SWR_MSTR_MAX_REG_ADDR 0x1740 #define SWR_MSTR_MAX_REG_ADDR 0x6B160A8
#define SWR_MSTR_START_REG_ADDR 0x00 #define SWR_MSTR_START_REG_ADDR 0x00
#define SWR_MSTR_MAX_BUF_LEN 32 #define SWR_MSTR_MAX_BUF_LEN 32
#define BYTES_PER_LINE 12 #define BYTES_PER_LINE 12
@@ -67,13 +67,6 @@ enum {
SWR_IRQ_REGISTER, SWR_IRQ_REGISTER,
}; };
enum {
SWR_DAC_PORT,
SWR_COMP_PORT,
SWR_BOOST_PORT,
SWR_VISENSE_PORT,
};
enum { enum {
SWR_PDM = 0, SWR_PDM = 0,
SWR_PCM, SWR_PCM,