Merge "msm: camera: isp: Add support for MMU prefetch for IFE/SFE WMs" into camera-kernel.lnx.5.0

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.c

@@ -6230,6 +6230,20 @@ static int cam_ife_mgr_start_hw(void *hw_mgr_priv, void *start_hw_args)
 		}
 	}
 
+	/* set IFE bus WR MMU config */
+	for (i = 0; i < CAM_IFE_HW_NUM_MAX; i++) {
+		if (g_ife_hw_mgr.ife_devices[i]) {
+			rc = g_ife_hw_mgr.ife_devices[i]->hw_intf->hw_ops.process_cmd(
+				g_ife_hw_mgr.ife_devices[i]->hw_intf->hw_priv,
+				CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG,
+				&g_ife_hw_mgr.debug_cfg.disable_ife_mmu_prefetch,
+				sizeof(g_ife_hw_mgr.debug_cfg.disable_ife_mmu_prefetch));
+			if (rc)
+				CAM_DBG(CAM_ISP,
+					"Failed to set IFE_%d bus wr debug cfg", i);
+		}
+	}
+
 	if (ctx->flags.need_csid_top_cfg) {
 		list_for_each_entry(hw_mgr_res, &ctx->res_list_ife_csid,
 				list) {
@@ -11191,6 +11205,9 @@ static int cam_ife_hw_mgr_debug_register(void)
 		g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_sfe_debug);
 	dbgfileptr = debugfs_create_file("sfe_sensor_diag_sel", 0644,
 		g_ife_hw_mgr.debug_cfg.dentry, NULL, &cam_ife_sfe_sensor_diag_debug);
+	dbgfileptr = debugfs_create_bool("disable_ife_mmu_prefetch", 0644,
+		g_ife_hw_mgr.debug_cfg.dentry,
+		&g_ife_hw_mgr.debug_cfg.disable_ife_mmu_prefetch);
 
 	if (IS_ERR(dbgfileptr)) {
 		if (PTR_ERR(dbgfileptr) == -ENODEV)

drivers/cam_isp/isp_hw_mgr/cam_ife_hw_mgr.h

@@ -50,6 +50,7 @@ enum cam_ife_ctx_master_type {
  * @enable_req_dump:           Enable request dump on HW errors
  * @per_req_reg_dump:          Enable per request reg dump
  * @disable_ubwc_comp:         Disable UBWC compression
+ * @disable_ife_mmu_prefetch:  Disable MMU prefetch for IFE bus WR
  *
  */
 struct cam_ife_hw_mgr_debug {
@@ -63,6 +64,7 @@ struct cam_ife_hw_mgr_debug {
 	bool           enable_req_dump;
 	bool           per_req_reg_dump;
 	bool           disable_ubwc_comp;
+	bool           disable_ife_mmu_prefetch;
 };
 
 /**

drivers/cam_isp/isp_hw_mgr/isp_hw/include/cam_isp_hw.h

@@ -156,6 +156,7 @@ enum cam_isp_hw_cmd_type {
 	CAM_ISP_HW_NOTIFY_OVERFLOW,
 	CAM_ISP_HW_CMD_IS_PDAF_RDI2_MUX_EN,
 	CAM_ISP_HW_CMD_GET_PATH_PORT_MAP,
+	CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG,
 	CAM_ISP_HW_CMD_MAX,
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe680.h

@@ -420,6 +420,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00000A80,
 			.debug_status_0           = 0x00000A84,
 			.debug_status_1           = 0x00000A88,
+			.mmu_prefetch_cfg         = 0x00000A60,
+			.mmu_prefetch_max_offset  = 0x00000A64,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_0,
 		},
 		/* BUS Client 1 LCR */
@@ -447,6 +449,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00000B80,
 			.debug_status_0           = 0x00000B84,
 			.debug_status_1           = 0x00000B88,
+			.mmu_prefetch_cfg         = 0x00000B60,
+			.mmu_prefetch_max_offset  = 0x00000B64,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_1,
 		},
 		/* BUS Client 2 STATS_BE_0 */
@@ -474,6 +478,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00000C80,
 			.debug_status_0           = 0x00000C84,
 			.debug_status_1           = 0x00000C88,
+			.mmu_prefetch_cfg         = 0x00000C60,
+			.mmu_prefetch_max_offset  = 0x00000C64,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_2,
 		},
 		/* BUS Client 3 STATS_BHIST_0 */
@@ -501,6 +507,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00000D80,
 			.debug_status_0           = 0x00000D84,
 			.debug_status_1           = 0x00000D88,
+			.mmu_prefetch_cfg         = 0x00000D60,
+			.mmu_prefetch_max_offset  = 0x00000D64,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_2,
 		},
 		/* BUS Client 4 STATS_BE_1 */
@@ -528,6 +536,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00000E80,
 			.debug_status_0           = 0x00000E84,
 			.debug_status_1           = 0x00000E88,
+			.mmu_prefetch_cfg         = 0x00000E60,
+			.mmu_prefetch_max_offset  = 0x00000E64,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_3,
 		},
 		/* BUS Client 5 STATS_BHIST_1 */
@@ -555,6 +565,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00000F80,
 			.debug_status_0           = 0x00000F84,
 			.debug_status_1           = 0x00000F88,
+			.mmu_prefetch_cfg         = 0x00000F60,
+			.mmu_prefetch_max_offset  = 0x00000F64,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_3,
 		},
 		/* BUS Client 6 STATS_BE_2 */
@@ -582,6 +594,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00001080,
 			.debug_status_0           = 0x00001084,
 			.debug_status_1           = 0x00001088,
+			.mmu_prefetch_cfg         = 0x00001060,
+			.mmu_prefetch_max_offset  = 0x00001064,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_4,
 		},
 		/* BUS Client 7 STATS_BHIST_2 */
@@ -609,6 +623,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00001180,
 			.debug_status_0           = 0x00001184,
 			.debug_status_1           = 0x00001188,
+			.mmu_prefetch_cfg         = 0x00001160,
+			.mmu_prefetch_max_offset  = 0x00001164,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_4,
 		},
 		/* BUS Client 8 RDI0 */
@@ -636,6 +652,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00001280,
 			.debug_status_0           = 0x00001284,
 			.debug_status_1           = 0x00001288,
+			.mmu_prefetch_cfg         = 0x00001260,
+			.mmu_prefetch_max_offset  = 0x00001264,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_5,
 		},
 		/* BUS Client 9 RDI1 */
@@ -663,6 +681,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00001380,
 			.debug_status_0           = 0x00001384,
 			.debug_status_1           = 0x00001388,
+			.mmu_prefetch_cfg         = 0x00001360,
+			.mmu_prefetch_max_offset  = 0x00001364,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_6,
 		},
 		/* BUS Client 10 RDI2 */
@@ -690,6 +710,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00001480,
 			.debug_status_0           = 0x00001484,
 			.debug_status_1           = 0x00001488,
+			.mmu_prefetch_cfg         = 0x00001460,
+			.mmu_prefetch_max_offset  = 0x00001464,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_7,
 		},
 		/* BUS Client 11 RDI3 */
@@ -717,6 +739,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00001580,
 			.debug_status_0           = 0x00001584,
 			.debug_status_1           = 0x00001588,
+			.mmu_prefetch_cfg         = 0x00001560,
+			.mmu_prefetch_max_offset  = 0x00001564,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_8,
 		},
 		/* BUS Client 12 RDI4 */
@@ -744,6 +768,8 @@ static struct cam_sfe_bus_wr_hw_info sfe680_bus_wr_hw_info = {
 			.debug_status_cfg         = 0x00001680,
 			.debug_status_0           = 0x00001684,
 			.debug_status_1           = 0x00001688,
+			.mmu_prefetch_cfg         = 0x00001660,
+			.mmu_prefetch_max_offset  = 0x00001664,
 			.comp_group               = CAM_SFE_BUS_WR_COMP_GRP_9,
 		},
 	},

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/cam_sfe_core.h

@@ -44,6 +44,7 @@ struct cam_sfe_hw_core_info {
 #define SFE_DEBUG_ENABLE_SENSOR_DIAG_INFO         BIT(1)
 #define SFE_DEBUG_ENABLE_FRAME_COUNTER            BIT(2)
 #define SFE_DEBUG_ENABLE_RD_DONE_IRQ              BIT(3)
+#define SFE_DEBUG_DISABLE_MMU_PREFETCH            BIT(4)
 
 int cam_sfe_get_hw_caps(void *device_priv,
 	void *get_hw_cap_args, uint32_t arg_size);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.c

@@ -734,6 +734,16 @@ static int cam_sfe_bus_start_wm(struct cam_isp_resource_node *wm_res)
 			rsrc_data->hw_regs->line_done_cfg);
 	}
 
+	if (!(common_data->sfe_debug_cfg & SFE_DEBUG_DISABLE_MMU_PREFETCH)) {
+		cam_io_w_mb(1, common_data->mem_base +
+			rsrc_data->hw_regs->mmu_prefetch_cfg);
+		cam_io_w_mb(0xFFFFFFFF, common_data->mem_base +
+			rsrc_data->hw_regs->mmu_prefetch_max_offset);
+		CAM_DBG(CAM_SFE, "SFE: %u WM: %u MMU prefetch enabled",
+			rsrc_data->common_data->core_index,
+			rsrc_data->index);
+	}
+
 	/* Enable WM */
 	cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base +
 		rsrc_data->hw_regs->cfg);

drivers/cam_isp/isp_hw_mgr/isp_hw/sfe_hw/sfe_bus/cam_sfe_bus_wr.h

@@ -114,6 +114,8 @@ struct cam_sfe_bus_reg_offset_bus_client {
 	uint32_t debug_status_cfg;
 	uint32_t debug_status_0;
 	uint32_t debug_status_1;
+	uint32_t mmu_prefetch_cfg;
+	uint32_t mmu_prefetch_max_offset;
 	uint32_t comp_group;
 };
 

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/cam_vfe_core.c

@@ -531,6 +531,7 @@ int cam_vfe_process_cmd(void *hw_priv, uint32_t cmd_type,
 	case CAM_ISP_HW_CMD_DUMP_BUS_INFO:
 	case CAM_ISP_HW_CMD_GET_RES_FOR_MID:
 	case CAM_ISP_HW_CMD_QUERY_BUS_CAP:
+	case CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG:
 		rc = core_info->vfe_bus->hw_ops.process_cmd(
 			core_info->vfe_bus->bus_priv, cmd_type, cmd_args,
 			arg_size);

drivers/cam_isp/isp_hw_mgr/isp_hw/vfe_hw/vfe_bus/cam_vfe_bus_ver3.c

@@ -100,6 +100,7 @@ struct cam_vfe_bus_ver3_common_data {
 	bool                                        support_consumed_addr;
 	bool                                        disable_ubwc_comp;
 	bool                                        init_irq_subscribed;
+	bool                                        disable_mmu_prefetch;
 	cam_hw_mgr_event_cb_func                    event_cb;
 	int                        rup_irq_handle[CAM_VFE_BUS_VER3_SRC_GRP_MAX];
 	uint32_t                                    pack_align_shift;
@@ -1248,6 +1249,18 @@ static int cam_vfe_bus_ver3_start_wm(struct cam_isp_resource_node *wm_res)
 		cam_io_w_mb(val, common_data->mem_base + ubwc_regs->mode_cfg);
 	}
 
+	/* Validate for debugfs and mmu reg info for targets that don't list it */
+	if (!(common_data->disable_mmu_prefetch) &&
+		(rsrc_data->hw_regs->mmu_prefetch_cfg)) {
+		cam_io_w_mb(1, common_data->mem_base +
+			rsrc_data->hw_regs->mmu_prefetch_cfg);
+		cam_io_w_mb(0xFFFFFFFF, common_data->mem_base +
+			rsrc_data->hw_regs->mmu_prefetch_max_offset);
+		CAM_DBG(CAM_SFE, "VFE: %d WM: %d MMU prefetch enabled",
+			rsrc_data->common_data->core_index,
+			rsrc_data->index);
+	}
+
 	/* Enable WM */
 	cam_io_w_mb(rsrc_data->en_cfg, common_data->mem_base +
 		rsrc_data->hw_regs->cfg);
@@ -3610,6 +3623,14 @@ static int cam_vfe_bus_ver3_process_cmd(
 		vfe_bus_cap->support_consumed_addr =
 			bus_priv->common_data.support_consumed_addr;
 		break;
+	case CAM_ISP_HW_CMD_IFE_BUS_DEBUG_CFG:
+		bus_priv = (struct cam_vfe_bus_ver3_priv  *) priv;
+		bus_priv->common_data.disable_mmu_prefetch =
+			(*((bool *)cmd_args));
+		CAM_DBG(CAM_ISP, "IFE bus WR prefetch %s",
+			bus_priv->common_data.disable_mmu_prefetch ?
+			"disabled" : "enabled");
+		break;
 	default:
 		CAM_ERR_RATE_LIMIT(CAM_ISP, "Invalid camif process command:%d",
 			cmd_type);
@@ -3691,6 +3712,7 @@ int cam_vfe_bus_ver3_init(
 	bus_priv->common_data.comp_config_needed =
 		ver3_hw_info->comp_cfg_needed;
 	bus_priv->common_data.init_irq_subscribed = false;
+	bus_priv->common_data.disable_mmu_prefetch = false;
 	bus_priv->common_data.pack_align_shift =
 		ver3_hw_info->pack_align_shift;
 	bus_priv->constraint_error_list = ver3_hw_info->constraint_error_list;