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@@ -87,6 +87,9 @@
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#define PLL_PLL_INT_GAIN_IFILT_BAND_1 0x15c
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#define PLL_PLL_INT_GAIN_IFILT_BAND_1 0x15c
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#define PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x164
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#define PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x164
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#define PLL_FASTLOCK_EN_BAND 0x16c
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#define PLL_FASTLOCK_EN_BAND 0x16c
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+#define PLL_FREQ_TUNE_ACCUM_INIT_LOW 0x170
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+#define PLL_FREQ_TUNE_ACCUM_INIT_MID 0x174
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+#define PLL_FREQ_TUNE_ACCUM_INIT_HIGH 0x178
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#define PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x17c
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#define PLL_FREQ_TUNE_ACCUM_INIT_MUX 0x17c
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#define PLL_PLL_LOCK_OVERRIDE 0x180
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#define PLL_PLL_LOCK_OVERRIDE 0x180
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#define PLL_PLL_LOCK_DELAY 0x184
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#define PLL_PLL_LOCK_DELAY 0x184
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@@ -104,6 +107,7 @@
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#define PHY_CMN_RBUF_CTRL 0x01c
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#define PHY_CMN_RBUF_CTRL 0x01c
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#define PHY_CMN_PLL_CNTRL 0x038
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#define PHY_CMN_PLL_CNTRL 0x038
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#define PHY_CMN_CTRL_0 0x024
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#define PHY_CMN_CTRL_0 0x024
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+#define PHY_CMN_CTRL_2 0x02c
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/* Bit definition of SSC control registers */
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/* Bit definition of SSC control registers */
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#define SSC_CENTER BIT(0)
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#define SSC_CENTER BIT(0)
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@@ -115,6 +119,43 @@
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#define SSC_START BIT(6)
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#define SSC_START BIT(6)
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#define SSC_START_MUX BIT(7)
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#define SSC_START_MUX BIT(7)
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+/* Dynamic Refresh Control Registers */
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL0 (0x014)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL1 (0x018)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL2 (0x01C)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL3 (0x020)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL4 (0x024)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL5 (0x028)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL6 (0x02C)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL7 (0x030)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL8 (0x034)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL9 (0x038)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL10 (0x03C)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL11 (0x040)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL12 (0x044)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL13 (0x048)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL14 (0x04C)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL15 (0x050)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL16 (0x054)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL17 (0x058)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL18 (0x05C)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL19 (0x060)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL20 (0x064)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL21 (0x068)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL22 (0x06C)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL23 (0x070)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL24 (0x074)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL25 (0x078)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL26 (0x07C)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL27 (0x080)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL28 (0x084)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL29 (0x088)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL30 (0x08C)
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+#define DSI_DYNAMIC_REFRESH_PLL_CTRL31 (0x090)
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+#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR (0x094)
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+#define DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2 (0x098)
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+
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+#define DSI_PHY_TO_PLL_OFFSET (0x600)
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enum {
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enum {
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DSI_PLL_0,
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DSI_PLL_0,
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DSI_PLL_1,
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DSI_PLL_1,
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@@ -621,6 +662,7 @@ static int vco_10nm_set_rate(struct clk_hw *hw, unsigned long rate,
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rsc->vco_current_rate = rate;
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rsc->vco_current_rate = rate;
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rsc->vco_ref_clk_rate = vco->ref_clk_rate;
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rsc->vco_ref_clk_rate = vco->ref_clk_rate;
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+ rsc->dfps_trigger = false;
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rc = mdss_pll_resource_enable(rsc, true);
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rc = mdss_pll_resource_enable(rsc, true);
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if (rc) {
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if (rc) {
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@@ -651,6 +693,237 @@ static int vco_10nm_set_rate(struct clk_hw *hw, unsigned long rate,
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return 0;
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return 0;
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}
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}
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+static int dsi_pll_read_stored_trim_codes(struct mdss_pll_resources *pll_res,
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+ unsigned long vco_clk_rate)
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+{
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+ int i;
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+ bool found = false;
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+
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+ if (!pll_res->dfps)
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+ return -EINVAL;
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+
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+ for (i = 0; i < pll_res->dfps->vco_rate_cnt; i++) {
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+ struct dfps_codes_info *codes_info =
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+ &pll_res->dfps->codes_dfps[i];
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+
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+ pr_debug("valid=%d vco_rate=%d, code %d %d %d\n",
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+ codes_info->is_valid, codes_info->clk_rate,
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+ codes_info->pll_codes.pll_codes_1,
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+ codes_info->pll_codes.pll_codes_2,
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+ codes_info->pll_codes.pll_codes_3);
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+
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+ if (vco_clk_rate != codes_info->clk_rate &&
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+ codes_info->is_valid)
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+ continue;
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+
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+ pll_res->cache_pll_trim_codes[0] =
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+ codes_info->pll_codes.pll_codes_1;
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+ pll_res->cache_pll_trim_codes[1] =
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+ codes_info->pll_codes.pll_codes_2;
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+ pll_res->cache_pll_trim_codes[2] =
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+ codes_info->pll_codes.pll_codes_3;
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+ found = true;
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+ break;
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+ }
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+
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+ if (!found)
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+ return -EINVAL;
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+
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+ pr_debug("trim_code_0=0x%x trim_code_1=0x%x trim_code_2=0x%x\n",
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+ pll_res->cache_pll_trim_codes[0],
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+ pll_res->cache_pll_trim_codes[1],
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+ pll_res->cache_pll_trim_codes[2]);
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+
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+ return 0;
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+}
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+
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+static void shadow_dsi_pll_dynamic_refresh_10nm(struct dsi_pll_10nm *pll,
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+ struct mdss_pll_resources *rsc)
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+{
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+ u32 data;
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+ u32 offset = DSI_PHY_TO_PLL_OFFSET;
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+ u32 upper_addr = 0;
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+ struct dsi_pll_regs *reg = &pll->reg_setup;
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+
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+ data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1);
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+ data &= ~BIT(5);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL0,
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+ PHY_CMN_CLK_CFG1, PHY_CMN_PLL_CNTRL, data, 0);
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+ upper_addr |= (upper_8_bit(PHY_CMN_CLK_CFG1) << 0);
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+ upper_addr |= (upper_8_bit(PHY_CMN_PLL_CNTRL) << 1);
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+
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL1,
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+ PHY_CMN_RBUF_CTRL,
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+ (PLL_DECIMAL_DIV_START_1 + offset),
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+ 0, reg->decimal_div_start);
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+ upper_addr |= (upper_8_bit(PHY_CMN_RBUF_CTRL) << 2);
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+ upper_addr |= (upper_8_bit(PLL_DECIMAL_DIV_START_1 + offset) << 3);
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+
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL2,
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+ (PLL_FRAC_DIV_START_LOW_1 + offset),
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+ (PLL_FRAC_DIV_START_MID_1 + offset),
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+ reg->frac_div_start_low, reg->frac_div_start_mid);
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+ upper_addr |= (upper_8_bit(PLL_FRAC_DIV_START_LOW_1 + offset) << 4);
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+ upper_addr |= (upper_8_bit(PLL_FRAC_DIV_START_MID_1 + offset) << 5);
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+
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL3,
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+ (PLL_FRAC_DIV_START_HIGH_1 + offset),
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+ (PLL_PLL_PROP_GAIN_RATE_1 + offset),
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+ reg->frac_div_start_high, reg->pll_prop_gain_rate);
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+ upper_addr |= (upper_8_bit(PLL_FRAC_DIV_START_HIGH_1 + offset) << 6);
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+ upper_addr |= (upper_8_bit(PLL_PLL_PROP_GAIN_RATE_1 + offset) << 7);
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+
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+ data = MDSS_PLL_REG_R(rsc->pll_base, PLL_PLL_OUTDIV_RATE) & 0x03;
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL4,
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+ (PLL_PLL_OUTDIV_RATE + offset),
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+ (PLL_FREQ_TUNE_ACCUM_INIT_LOW + offset),
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+ data, 0);
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+ upper_addr |= (upper_8_bit(PLL_PLL_OUTDIV_RATE + offset) << 8);
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+ upper_addr |= (upper_8_bit(PLL_FREQ_TUNE_ACCUM_INIT_LOW + offset) << 9);
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+
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL5,
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+ (PLL_FREQ_TUNE_ACCUM_INIT_MID + offset),
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+ (PLL_FREQ_TUNE_ACCUM_INIT_HIGH + offset),
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+ rsc->cache_pll_trim_codes[1],
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+ rsc->cache_pll_trim_codes[0]);
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+ upper_addr |=
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+ (upper_8_bit(PLL_FREQ_TUNE_ACCUM_INIT_MID + offset) << 10);
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+ upper_addr |=
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+ (upper_8_bit(PLL_FREQ_TUNE_ACCUM_INIT_HIGH + offset) << 11);
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+
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL6,
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+ (PLL_FREQ_TUNE_ACCUM_INIT_MUX + offset),
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+ (PLL_PLL_BAND_SET_RATE_1 + offset),
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+ 0x07, rsc->cache_pll_trim_codes[2]);
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+ upper_addr |=
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+ (upper_8_bit(PLL_FREQ_TUNE_ACCUM_INIT_MUX + offset) << 12);
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+ upper_addr |= (upper_8_bit(PLL_PLL_BAND_SET_RATE_1 + offset) << 13);
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+
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL7,
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+ (PLL_CALIBRATION_SETTINGS + offset),
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+ (PLL_BAND_SEL_CAL_SETTINGS + offset), 0x44, 0x3a);
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+ upper_addr |= (upper_8_bit(PLL_CALIBRATION_SETTINGS + offset) << 14);
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+ upper_addr |= (upper_8_bit(PLL_BAND_SEL_CAL_SETTINGS + offset) << 15);
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+
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL8,
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+ (PLL_PLL_LOCKDET_RATE_1 + offset),
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+ (PLL_PLL_LOCK_DELAY + offset), 0x10, 0x06);
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+ upper_addr |= (upper_8_bit(PLL_PLL_LOCKDET_RATE_1 + offset) << 16);
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+ upper_addr |= (upper_8_bit(PLL_PLL_LOCK_DELAY + offset) << 17);
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+
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+ data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG0);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL17,
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+ PHY_CMN_CTRL_2, PHY_CMN_CLK_CFG0, 0x40, data);
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+ if (rsc->slave)
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+ MDSS_DYN_PLL_REG_W(rsc->slave->dyn_pll_base,
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+ DSI_DYNAMIC_REFRESH_PLL_CTRL10,
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+ PHY_CMN_CLK_CFG0, PHY_CMN_CTRL_0,
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+ data, 0x7f);
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+
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL18,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ /* Dummy register writes */
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL19,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL20,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL21,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL22,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL23,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL24,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL25,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL26,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL27,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL28,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL29,
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+ PHY_CMN_PLL_CNTRL, PHY_CMN_PLL_CNTRL, 0x01, 0x01);
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+
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+ /* Registers to configure after PLL enable delay */
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+ data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CLK_CFG1) | BIT(5);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL30,
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+ PHY_CMN_CLK_CFG1, PHY_CMN_RBUF_CTRL, data, 0x01);
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+ MDSS_DYN_PLL_REG_W(rsc->dyn_pll_base, DSI_DYNAMIC_REFRESH_PLL_CTRL31,
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+ PHY_CMN_CLK_CFG1, PHY_CMN_CLK_CFG1, data, data);
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+ if (rsc->slave) {
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+ data = MDSS_PLL_REG_R(rsc->slave->phy_base, PHY_CMN_CLK_CFG1) |
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+ BIT(5);
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+ MDSS_DYN_PLL_REG_W(rsc->slave->dyn_pll_base,
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+ DSI_DYNAMIC_REFRESH_PLL_CTRL30,
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+ PHY_CMN_CLK_CFG1, PHY_CMN_RBUF_CTRL,
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+ data, 0x01);
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|
+ MDSS_DYN_PLL_REG_W(rsc->slave->dyn_pll_base,
|
|
|
|
+ DSI_DYNAMIC_REFRESH_PLL_CTRL31,
|
|
|
|
+ PHY_CMN_CLK_CFG1, PHY_CMN_CLK_CFG1,
|
|
|
|
+ data, data);
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ MDSS_PLL_REG_W(rsc->dyn_pll_base,
|
|
|
|
+ DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR, upper_addr);
|
|
|
|
+ MDSS_PLL_REG_W(rsc->dyn_pll_base,
|
|
|
|
+ DSI_DYNAMIC_REFRESH_PLL_UPPER_ADDR2, 0);
|
|
|
|
+ wmb(); /* commit register writes */
|
|
|
|
+}
|
|
|
|
+
|
|
|
|
+static int shadow_vco_10nm_set_rate(struct clk_hw *hw, unsigned long rate,
|
|
|
|
+ unsigned long parent_rate)
|
|
|
|
+{
|
|
|
|
+ int rc;
|
|
|
|
+ struct dsi_pll_10nm *pll;
|
|
|
|
+ struct dsi_pll_vco_clk *vco = to_vco_clk_hw(hw);
|
|
|
|
+ struct mdss_pll_resources *rsc = vco->priv;
|
|
|
|
+
|
|
|
|
+ if (!rsc) {
|
|
|
|
+ pr_err("pll resource not found\n");
|
|
|
|
+ return -EINVAL;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ pll = rsc->priv;
|
|
|
|
+ if (!pll) {
|
|
|
|
+ pr_err("pll configuration not found\n");
|
|
|
|
+ return -EINVAL;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ rc = dsi_pll_read_stored_trim_codes(rsc, rate);
|
|
|
|
+ if (rc) {
|
|
|
|
+ pr_err("cannot find pll codes rate=%ld\n", rate);
|
|
|
|
+ return -EINVAL;
|
|
|
|
+ }
|
|
|
|
+ pr_debug("ndx=%d, rate=%lu\n", rsc->index, rate);
|
|
|
|
+
|
|
|
|
+ rsc->vco_current_rate = rate;
|
|
|
|
+ rsc->vco_ref_clk_rate = vco->ref_clk_rate;
|
|
|
|
+
|
|
|
|
+ rc = mdss_pll_resource_enable(rsc, true);
|
|
|
|
+ if (rc) {
|
|
|
|
+ pr_err("failed to enable mdss dsi pll(%d), rc=%d\n",
|
|
|
|
+ rsc->index, rc);
|
|
|
|
+ return rc;
|
|
|
|
+ }
|
|
|
|
+
|
|
|
|
+ dsi_pll_setup_config(pll, rsc);
|
|
|
|
+
|
|
|
|
+ dsi_pll_calc_dec_frac(pll, rsc);
|
|
|
|
+
|
|
|
|
+ /* program dynamic refresh control registers */
|
|
|
|
+ shadow_dsi_pll_dynamic_refresh_10nm(pll, rsc);
|
|
|
|
+
|
|
|
|
+ /* update cached vco rate */
|
|
|
|
+ rsc->vco_cached_rate = rate;
|
|
|
|
+ rsc->dfps_trigger = true;
|
|
|
|
+
|
|
|
|
+ mdss_pll_resource_enable(rsc, false);
|
|
|
|
+
|
|
|
|
+ return 0;
|
|
|
|
+}
|
|
|
|
+
|
|
static int dsi_pll_10nm_lock_status(struct mdss_pll_resources *pll)
|
|
static int dsi_pll_10nm_lock_status(struct mdss_pll_resources *pll)
|
|
{
|
|
{
|
|
int rc;
|
|
int rc;
|
|
@@ -716,7 +989,7 @@ static int dsi_pll_enable(struct dsi_pll_vco_clk *vco)
|
|
phy_reg_update_bits_sub(rsc, PHY_CMN_CLK_CFG1, 0x03, rsc->cached_cfg1);
|
|
phy_reg_update_bits_sub(rsc, PHY_CMN_CLK_CFG1, 0x03, rsc->cached_cfg1);
|
|
if (rsc->slave)
|
|
if (rsc->slave)
|
|
phy_reg_update_bits_sub(rsc->slave, PHY_CMN_CLK_CFG1,
|
|
phy_reg_update_bits_sub(rsc->slave, PHY_CMN_CLK_CFG1,
|
|
- 0x03, rsc->cached_cfg1);
|
|
|
|
|
|
+ 0x03, rsc->slave->cached_cfg1);
|
|
wmb(); /* ensure dsiclk_sel is always programmed before pll start */
|
|
wmb(); /* ensure dsiclk_sel is always programmed before pll start */
|
|
|
|
|
|
/* Start PLL */
|
|
/* Start PLL */
|
|
@@ -766,6 +1039,7 @@ static void dsi_pll_disable(struct dsi_pll_vco_clk *vco)
|
|
}
|
|
}
|
|
|
|
|
|
rsc->handoff_resources = false;
|
|
rsc->handoff_resources = false;
|
|
|
|
+ rsc->dfps_trigger = false;
|
|
|
|
|
|
pr_debug("stop PLL (%d)\n", rsc->index);
|
|
pr_debug("stop PLL (%d)\n", rsc->index);
|
|
|
|
|
|
@@ -817,16 +1091,18 @@ static void vco_10nm_unprepare(struct clk_hw *hw)
|
|
/*
|
|
/*
|
|
* During unprepare in continuous splash use case we want driver
|
|
* During unprepare in continuous splash use case we want driver
|
|
* to pick all dividers instead of retaining bootloader configurations.
|
|
* to pick all dividers instead of retaining bootloader configurations.
|
|
|
|
+ * Also handle use cases where dynamic refresh triggered before
|
|
|
|
+ * first suspend/resume.
|
|
*/
|
|
*/
|
|
- if (!pll->handoff_resources) {
|
|
|
|
|
|
+ if (!pll->handoff_resources || pll->dfps_trigger) {
|
|
pll->cached_cfg0 = MDSS_PLL_REG_R(pll->phy_base,
|
|
pll->cached_cfg0 = MDSS_PLL_REG_R(pll->phy_base,
|
|
- PHY_CMN_CLK_CFG0);
|
|
|
|
|
|
+ PHY_CMN_CLK_CFG0);
|
|
pll->cached_outdiv = MDSS_PLL_REG_R(pll->pll_base,
|
|
pll->cached_outdiv = MDSS_PLL_REG_R(pll->pll_base,
|
|
- PLL_PLL_OUTDIV_RATE);
|
|
|
|
|
|
+ PLL_PLL_OUTDIV_RATE);
|
|
pr_debug("cfg0=%d,cfg1=%d, outdiv=%d\n", pll->cached_cfg0,
|
|
pr_debug("cfg0=%d,cfg1=%d, outdiv=%d\n", pll->cached_cfg0,
|
|
- pll->cached_cfg1, pll->cached_outdiv);
|
|
|
|
|
|
+ pll->cached_cfg1, pll->cached_outdiv);
|
|
|
|
|
|
- pll->vco_cached_rate = clk_hw_get_rate(hw);
|
|
|
|
|
|
+ pll->vco_cached_rate = clk_get_rate(hw->clk);
|
|
}
|
|
}
|
|
|
|
|
|
/*
|
|
/*
|
|
@@ -836,9 +1112,15 @@ static void vco_10nm_unprepare(struct clk_hw *hw)
|
|
* does not change.For such usecases, we need to ensure that the cached
|
|
* does not change.For such usecases, we need to ensure that the cached
|
|
* value is programmed prior to PLL being locked
|
|
* value is programmed prior to PLL being locked
|
|
*/
|
|
*/
|
|
- if (pll->handoff_resources)
|
|
|
|
|
|
+ if (pll->handoff_resources) {
|
|
pll->cached_cfg1 = MDSS_PLL_REG_R(pll->phy_base,
|
|
pll->cached_cfg1 = MDSS_PLL_REG_R(pll->phy_base,
|
|
- PHY_CMN_CLK_CFG1);
|
|
|
|
|
|
+ PHY_CMN_CLK_CFG1);
|
|
|
|
+ if (pll->slave)
|
|
|
|
+ pll->slave->cached_cfg1 =
|
|
|
|
+ MDSS_PLL_REG_R(pll->slave->phy_base,
|
|
|
|
+ PHY_CMN_CLK_CFG1);
|
|
|
|
+ }
|
|
|
|
+
|
|
dsi_pll_disable(vco);
|
|
dsi_pll_disable(vco);
|
|
mdss_pll_resource_enable(pll, false);
|
|
mdss_pll_resource_enable(pll, false);
|
|
}
|
|
}
|
|
@@ -866,7 +1148,7 @@ static int vco_10nm_prepare(struct clk_hw *hw)
|
|
}
|
|
}
|
|
|
|
|
|
if ((pll->vco_cached_rate != 0) &&
|
|
if ((pll->vco_cached_rate != 0) &&
|
|
- (pll->vco_cached_rate == clk_hw_get_rate(hw))) {
|
|
|
|
|
|
+ (pll->vco_cached_rate == clk_get_rate(hw->clk))) {
|
|
rc = hw->init->ops->set_rate(hw, pll->vco_cached_rate,
|
|
rc = hw->init->ops->set_rate(hw, pll->vco_cached_rate,
|
|
pll->vco_cached_rate);
|
|
pll->vco_cached_rate);
|
|
if (rc) {
|
|
if (rc) {
|
|
@@ -879,6 +1161,9 @@ static int vco_10nm_prepare(struct clk_hw *hw)
|
|
pll->cached_cfg1);
|
|
pll->cached_cfg1);
|
|
MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0,
|
|
MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0,
|
|
pll->cached_cfg0);
|
|
pll->cached_cfg0);
|
|
|
|
+ if (pll->slave)
|
|
|
|
+ MDSS_PLL_REG_W(pll->slave->phy_base, PHY_CMN_CLK_CFG0,
|
|
|
|
+ pll->cached_cfg0);
|
|
MDSS_PLL_REG_W(pll->pll_base, PLL_PLL_OUTDIV_RATE,
|
|
MDSS_PLL_REG_W(pll->pll_base, PLL_PLL_OUTDIV_RATE,
|
|
pll->cached_outdiv);
|
|
pll->cached_outdiv);
|
|
}
|
|
}
|
|
@@ -1014,6 +1299,14 @@ static void pixel_clk_set_div_sub(struct mdss_pll_resources *pll, int div)
|
|
reg_val &= ~0xF0;
|
|
reg_val &= ~0xF0;
|
|
reg_val |= (div << 4);
|
|
reg_val |= (div << 4);
|
|
MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0, reg_val);
|
|
MDSS_PLL_REG_W(pll->phy_base, PHY_CMN_CLK_CFG0, reg_val);
|
|
|
|
+
|
|
|
|
+ /*
|
|
|
|
+ * cache the current parent index for cases where parent
|
|
|
|
+ * is not changing but rate is changing. In that case
|
|
|
|
+ * clock framework won't call parent_set and hence dsiclk_sel
|
|
|
|
+ * bit won't be programmed. e.g. dfps update use case.
|
|
|
|
+ */
|
|
|
|
+ pll->cached_cfg0 = reg_val;
|
|
}
|
|
}
|
|
|
|
|
|
static int pixel_clk_set_div(void *context, unsigned int reg, unsigned int div)
|
|
static int pixel_clk_set_div(void *context, unsigned int reg, unsigned int div)
|
|
@@ -1151,6 +1444,12 @@ static const struct clk_ops clk_ops_vco_10nm = {
|
|
.unprepare = vco_10nm_unprepare,
|
|
.unprepare = vco_10nm_unprepare,
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static const struct clk_ops clk_ops_shadow_vco_10nm = {
|
|
|
|
+ .recalc_rate = vco_10nm_recalc_rate,
|
|
|
|
+ .set_rate = shadow_vco_10nm_set_rate,
|
|
|
|
+ .round_rate = vco_10nm_round_rate,
|
|
|
|
+};
|
|
|
|
+
|
|
static struct regmap_bus mdss_mux_regmap_bus = {
|
|
static struct regmap_bus mdss_mux_regmap_bus = {
|
|
.reg_write = mdss_set_mux_sel,
|
|
.reg_write = mdss_set_mux_sel,
|
|
.reg_read = mdss_get_mux_sel,
|
|
.reg_read = mdss_get_mux_sel,
|
|
@@ -1225,6 +1524,19 @@ static struct dsi_pll_vco_clk dsi0pll_vco_clk = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct dsi_pll_vco_clk dsi0pll_shadow_vco_clk = {
|
|
|
|
+ .ref_clk_rate = 19200000UL,
|
|
|
|
+ .min_rate = 1000000000UL,
|
|
|
|
+ .max_rate = 3500000000UL,
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi0pll_shadow_vco_clk",
|
|
|
|
+ .parent_names = (const char *[]){"bi_tcxo"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .ops = &clk_ops_shadow_vco_10nm,
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
|
|
static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
|
|
.ref_clk_rate = 19200000UL,
|
|
.ref_clk_rate = 19200000UL,
|
|
.min_rate = 1000000000UL,
|
|
.min_rate = 1000000000UL,
|
|
@@ -1238,6 +1550,19 @@ static struct dsi_pll_vco_clk dsi1pll_vco_clk = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct dsi_pll_vco_clk dsi1pll_shadow_vco_clk = {
|
|
|
|
+ .ref_clk_rate = 19200000UL,
|
|
|
|
+ .min_rate = 1000000000UL,
|
|
|
|
+ .max_rate = 3500000000UL,
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi1pll_shadow_vco_clk",
|
|
|
|
+ .parent_names = (const char *[]){"bi_tcxo"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .ops = &clk_ops_shadow_vco_10nm,
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_div dsi0pll_pll_out_div = {
|
|
static struct clk_regmap_div dsi0pll_pll_out_div = {
|
|
.reg = PLL_PLL_OUTDIV_RATE,
|
|
.reg = PLL_PLL_OUTDIV_RATE,
|
|
.shift = 0,
|
|
.shift = 0,
|
|
@@ -1254,6 +1579,23 @@ static struct clk_regmap_div dsi0pll_pll_out_div = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_regmap_div dsi0pll_shadow_pll_out_div = {
|
|
|
|
+ .reg = PLL_PLL_OUTDIV_RATE,
|
|
|
|
+ .shift = 0,
|
|
|
|
+ .width = 2,
|
|
|
|
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
|
|
|
|
+ .clkr = {
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi0pll_shadow_pll_out_div",
|
|
|
|
+ .parent_names = (const char *[]){
|
|
|
|
+ "dsi0pll_shadow_vco_clk"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
+ .ops = &clk_regmap_div_ops,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_div dsi1pll_pll_out_div = {
|
|
static struct clk_regmap_div dsi1pll_pll_out_div = {
|
|
.reg = PLL_PLL_OUTDIV_RATE,
|
|
.reg = PLL_PLL_OUTDIV_RATE,
|
|
.shift = 0,
|
|
.shift = 0,
|
|
@@ -1270,6 +1612,23 @@ static struct clk_regmap_div dsi1pll_pll_out_div = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_regmap_div dsi1pll_shadow_pll_out_div = {
|
|
|
|
+ .reg = PLL_PLL_OUTDIV_RATE,
|
|
|
|
+ .shift = 0,
|
|
|
|
+ .width = 2,
|
|
|
|
+ .flags = CLK_DIVIDER_POWER_OF_TWO,
|
|
|
|
+ .clkr = {
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi1pll_shadow_pll_out_div",
|
|
|
|
+ .parent_names = (const char *[]){
|
|
|
|
+ "dsi1pll_shadow_vco_clk"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
+ .ops = &clk_regmap_div_ops,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_div dsi0pll_bitclk_src = {
|
|
static struct clk_regmap_div dsi0pll_bitclk_src = {
|
|
.shift = 0,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.width = 4,
|
|
@@ -1284,6 +1643,21 @@ static struct clk_regmap_div dsi0pll_bitclk_src = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_regmap_div dsi0pll_shadow_bitclk_src = {
|
|
|
|
+ .shift = 0,
|
|
|
|
+ .width = 4,
|
|
|
|
+ .clkr = {
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi0pll_shadow_bitclk_src",
|
|
|
|
+ .parent_names = (const char *[]){
|
|
|
|
+ "dsi0pll_shadow_pll_out_div"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
+ .ops = &clk_regmap_div_ops,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_div dsi1pll_bitclk_src = {
|
|
static struct clk_regmap_div dsi1pll_bitclk_src = {
|
|
.shift = 0,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.width = 4,
|
|
@@ -1298,6 +1672,21 @@ static struct clk_regmap_div dsi1pll_bitclk_src = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_regmap_div dsi1pll_shadow_bitclk_src = {
|
|
|
|
+ .shift = 0,
|
|
|
|
+ .width = 4,
|
|
|
|
+ .clkr = {
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi1pll_shadow_bitclk_src",
|
|
|
|
+ .parent_names = (const char *[]){
|
|
|
|
+ "dsi1pll_shadow_pll_out_div"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
+ .ops = &clk_regmap_div_ops,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_fixed_factor dsi0pll_post_vco_div = {
|
|
static struct clk_fixed_factor dsi0pll_post_vco_div = {
|
|
.div = 4,
|
|
.div = 4,
|
|
.mult = 1,
|
|
.mult = 1,
|
|
@@ -1305,7 +1694,19 @@ static struct clk_fixed_factor dsi0pll_post_vco_div = {
|
|
.name = "dsi0pll_post_vco_div",
|
|
.name = "dsi0pll_post_vco_div",
|
|
.parent_names = (const char *[]){"dsi0pll_pll_out_div"},
|
|
.parent_names = (const char *[]){"dsi0pll_pll_out_div"},
|
|
.num_parents = 1,
|
|
.num_parents = 1,
|
|
- .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
|
|
+ .ops = &clk_fixed_factor_ops,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct clk_fixed_factor dsi0pll_shadow_post_vco_div = {
|
|
|
|
+ .div = 4,
|
|
|
|
+ .mult = 1,
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi0pll_shadow_post_vco_div",
|
|
|
|
+ .parent_names = (const char *[]){"dsi0pll_shadow_pll_out_div"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
.ops = &clk_fixed_factor_ops,
|
|
.ops = &clk_fixed_factor_ops,
|
|
},
|
|
},
|
|
};
|
|
};
|
|
@@ -1317,7 +1718,19 @@ static struct clk_fixed_factor dsi1pll_post_vco_div = {
|
|
.name = "dsi1pll_post_vco_div",
|
|
.name = "dsi1pll_post_vco_div",
|
|
.parent_names = (const char *[]){"dsi1pll_pll_out_div"},
|
|
.parent_names = (const char *[]){"dsi1pll_pll_out_div"},
|
|
.num_parents = 1,
|
|
.num_parents = 1,
|
|
- .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
|
|
+ .ops = &clk_fixed_factor_ops,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
|
|
+static struct clk_fixed_factor dsi1pll_shadow_post_vco_div = {
|
|
|
|
+ .div = 4,
|
|
|
|
+ .mult = 1,
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi1pll_shadow_post_vco_div",
|
|
|
|
+ .parent_names = (const char *[]){"dsi1pll_shadow_pll_out_div"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
.ops = &clk_fixed_factor_ops,
|
|
.ops = &clk_fixed_factor_ops,
|
|
},
|
|
},
|
|
};
|
|
};
|
|
@@ -1334,6 +1747,18 @@ static struct clk_fixed_factor dsi0pll_byteclk_src = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_fixed_factor dsi0pll_shadow_byteclk_src = {
|
|
|
|
+ .div = 8,
|
|
|
|
+ .mult = 1,
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi0pll_shadow_byteclk_src",
|
|
|
|
+ .parent_names = (const char *[]){"dsi0pll_shadow_bitclk_src"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
+ .ops = &clk_fixed_factor_ops,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_fixed_factor dsi1pll_byteclk_src = {
|
|
static struct clk_fixed_factor dsi1pll_byteclk_src = {
|
|
.div = 8,
|
|
.div = 8,
|
|
.mult = 1,
|
|
.mult = 1,
|
|
@@ -1346,6 +1771,18 @@ static struct clk_fixed_factor dsi1pll_byteclk_src = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_fixed_factor dsi1pll_shadow_byteclk_src = {
|
|
|
|
+ .div = 8,
|
|
|
|
+ .mult = 1,
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi1pll_shadow_byteclk_src",
|
|
|
|
+ .parent_names = (const char *[]){"dsi1pll_shadow_bitclk_src"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
+ .ops = &clk_fixed_factor_ops,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_fixed_factor dsi0pll_post_bit_div = {
|
|
static struct clk_fixed_factor dsi0pll_post_bit_div = {
|
|
.div = 2,
|
|
.div = 2,
|
|
.mult = 1,
|
|
.mult = 1,
|
|
@@ -1358,6 +1795,18 @@ static struct clk_fixed_factor dsi0pll_post_bit_div = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_fixed_factor dsi0pll_shadow_post_bit_div = {
|
|
|
|
+ .div = 2,
|
|
|
|
+ .mult = 1,
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi0pll_shadow_post_bit_div",
|
|
|
|
+ .parent_names = (const char *[]){"dsi0pll_shadow_bitclk_src"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
|
|
+ .ops = &clk_fixed_factor_ops,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_fixed_factor dsi1pll_post_bit_div = {
|
|
static struct clk_fixed_factor dsi1pll_post_bit_div = {
|
|
.div = 2,
|
|
.div = 2,
|
|
.mult = 1,
|
|
.mult = 1,
|
|
@@ -1370,15 +1819,29 @@ static struct clk_fixed_factor dsi1pll_post_bit_div = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_fixed_factor dsi1pll_shadow_post_bit_div = {
|
|
|
|
+ .div = 2,
|
|
|
|
+ .mult = 1,
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi1pll_shadow_post_bit_div",
|
|
|
|
+ .parent_names = (const char *[]){"dsi1pll_shadow_bitclk_src"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
|
|
+ .ops = &clk_fixed_factor_ops,
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_mux dsi0pll_byteclk_mux = {
|
|
static struct clk_regmap_mux dsi0pll_byteclk_mux = {
|
|
.shift = 0,
|
|
.shift = 0,
|
|
.width = 1,
|
|
.width = 1,
|
|
.clkr = {
|
|
.clkr = {
|
|
.hw.init = &(struct clk_init_data){
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "dsi0_phy_pll_out_byteclk",
|
|
.name = "dsi0_phy_pll_out_byteclk",
|
|
- .parent_names = (const char *[]){"dsi0pll_byteclk_src"},
|
|
|
|
- .num_parents = 1,
|
|
|
|
- .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
|
|
+ .parent_names = (const char *[]){"dsi0pll_byteclk_src",
|
|
|
|
+ "dsi0pll_shadow_byteclk_src"},
|
|
|
|
+ .num_parents = 2,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |
|
|
|
|
+ CLK_SET_RATE_NO_REPARENT),
|
|
.ops = &clk_regmap_mux_closest_ops,
|
|
.ops = &clk_regmap_mux_closest_ops,
|
|
},
|
|
},
|
|
},
|
|
},
|
|
@@ -1390,9 +1853,11 @@ static struct clk_regmap_mux dsi1pll_byteclk_mux = {
|
|
.clkr = {
|
|
.clkr = {
|
|
.hw.init = &(struct clk_init_data){
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "dsi1_phy_pll_out_byteclk",
|
|
.name = "dsi1_phy_pll_out_byteclk",
|
|
- .parent_names = (const char *[]){"dsi1pll_byteclk_src"},
|
|
|
|
- .num_parents = 1,
|
|
|
|
- .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
|
|
+ .parent_names = (const char *[]){"dsi1pll_byteclk_src",
|
|
|
|
+ "dsi1pll_shadow_byteclk_src"},
|
|
|
|
+ .num_parents = 2,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |
|
|
|
|
+ CLK_SET_RATE_NO_REPARENT),
|
|
.ops = &clk_regmap_mux_closest_ops,
|
|
.ops = &clk_regmap_mux_closest_ops,
|
|
},
|
|
},
|
|
},
|
|
},
|
|
@@ -1416,6 +1881,25 @@ static struct clk_regmap_mux dsi0pll_pclk_src_mux = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_regmap_mux dsi0pll_shadow_pclk_src_mux = {
|
|
|
|
+ .reg = PHY_CMN_CLK_CFG1,
|
|
|
|
+ .shift = 0,
|
|
|
|
+ .width = 2,
|
|
|
|
+ .clkr = {
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi0pll_shadow_pclk_src_mux",
|
|
|
|
+ .parent_names = (const char *[]){
|
|
|
|
+ "dsi0pll_shadow_bitclk_src",
|
|
|
|
+ "dsi0pll_shadow_post_bit_div",
|
|
|
|
+ "dsi0pll_shadow_pll_out_div",
|
|
|
|
+ "dsi0pll_shadow_post_vco_div"},
|
|
|
|
+ .num_parents = 4,
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
|
|
+ .ops = &clk_regmap_mux_closest_ops,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
|
|
static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
|
|
.reg = PHY_CMN_CLK_CFG1,
|
|
.reg = PHY_CMN_CLK_CFG1,
|
|
.shift = 0,
|
|
.shift = 0,
|
|
@@ -1434,6 +1918,25 @@ static struct clk_regmap_mux dsi1pll_pclk_src_mux = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_regmap_mux dsi1pll_shadow_pclk_src_mux = {
|
|
|
|
+ .reg = PHY_CMN_CLK_CFG1,
|
|
|
|
+ .shift = 0,
|
|
|
|
+ .width = 2,
|
|
|
|
+ .clkr = {
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi1pll_shadow_pclk_src_mux",
|
|
|
|
+ .parent_names = (const char *[]){
|
|
|
|
+ "dsi1pll_shadow_bitclk_src",
|
|
|
|
+ "dsi1pll_shadow_post_bit_div",
|
|
|
|
+ "dsi1pll_shadow_pll_out_div",
|
|
|
|
+ "dsi1pll_shadow_post_vco_div"},
|
|
|
|
+ .num_parents = 4,
|
|
|
|
+ .flags = CLK_GET_RATE_NOCACHE,
|
|
|
|
+ .ops = &clk_regmap_mux_closest_ops,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_div dsi0pll_pclk_src = {
|
|
static struct clk_regmap_div dsi0pll_pclk_src = {
|
|
.shift = 0,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.width = 4,
|
|
@@ -1449,6 +1952,21 @@ static struct clk_regmap_div dsi0pll_pclk_src = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_regmap_div dsi0pll_shadow_pclk_src = {
|
|
|
|
+ .shift = 0,
|
|
|
|
+ .width = 4,
|
|
|
|
+ .clkr = {
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi0pll_shadow_pclk_src",
|
|
|
|
+ .parent_names = (const char *[]){
|
|
|
|
+ "dsi0pll_shadow_pclk_src_mux"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
+ .ops = &clk_regmap_div_ops,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_div dsi1pll_pclk_src = {
|
|
static struct clk_regmap_div dsi1pll_pclk_src = {
|
|
.shift = 0,
|
|
.shift = 0,
|
|
.width = 4,
|
|
.width = 4,
|
|
@@ -1464,15 +1982,32 @@ static struct clk_regmap_div dsi1pll_pclk_src = {
|
|
},
|
|
},
|
|
};
|
|
};
|
|
|
|
|
|
|
|
+static struct clk_regmap_div dsi1pll_shadow_pclk_src = {
|
|
|
|
+ .shift = 0,
|
|
|
|
+ .width = 4,
|
|
|
|
+ .clkr = {
|
|
|
|
+ .hw.init = &(struct clk_init_data){
|
|
|
|
+ .name = "dsi1pll_shadow_pclk_src",
|
|
|
|
+ .parent_names = (const char *[]){
|
|
|
|
+ "dsi1pll_shadow_pclk_src_mux"},
|
|
|
|
+ .num_parents = 1,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
+ .ops = &clk_regmap_div_ops,
|
|
|
|
+ },
|
|
|
|
+ },
|
|
|
|
+};
|
|
|
|
+
|
|
static struct clk_regmap_mux dsi0pll_pclk_mux = {
|
|
static struct clk_regmap_mux dsi0pll_pclk_mux = {
|
|
.shift = 0,
|
|
.shift = 0,
|
|
.width = 1,
|
|
.width = 1,
|
|
.clkr = {
|
|
.clkr = {
|
|
.hw.init = &(struct clk_init_data){
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "dsi0_phy_pll_out_dsiclk",
|
|
.name = "dsi0_phy_pll_out_dsiclk",
|
|
- .parent_names = (const char *[]){"dsi0pll_pclk_src"},
|
|
|
|
- .num_parents = 1,
|
|
|
|
- .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
|
|
+ .parent_names = (const char *[]){"dsi0pll_pclk_src",
|
|
|
|
+ "dsi0pll_shadow_pclk_src"},
|
|
|
|
+ .num_parents = 2,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |
|
|
|
|
+ CLK_SET_RATE_NO_REPARENT),
|
|
.ops = &clk_regmap_mux_closest_ops,
|
|
.ops = &clk_regmap_mux_closest_ops,
|
|
},
|
|
},
|
|
},
|
|
},
|
|
@@ -1484,9 +2019,11 @@ static struct clk_regmap_mux dsi1pll_pclk_mux = {
|
|
.clkr = {
|
|
.clkr = {
|
|
.hw.init = &(struct clk_init_data){
|
|
.hw.init = &(struct clk_init_data){
|
|
.name = "dsi1_phy_pll_out_dsiclk",
|
|
.name = "dsi1_phy_pll_out_dsiclk",
|
|
- .parent_names = (const char *[]){"dsi1pll_pclk_src"},
|
|
|
|
- .num_parents = 1,
|
|
|
|
- .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT),
|
|
|
|
|
|
+ .parent_names = (const char *[]){"dsi1pll_pclk_src",
|
|
|
|
+ "dsi1pll_shadow_pclk_src"},
|
|
|
|
+ .num_parents = 2,
|
|
|
|
+ .flags = (CLK_GET_RATE_NOCACHE | CLK_SET_RATE_PARENT |
|
|
|
|
+ CLK_SET_RATE_NO_REPARENT),
|
|
.ops = &clk_regmap_mux_closest_ops,
|
|
.ops = &clk_regmap_mux_closest_ops,
|
|
},
|
|
},
|
|
},
|
|
},
|
|
@@ -1503,6 +2040,14 @@ static struct clk_hw *mdss_dsi_pllcc_10nm[] = {
|
|
[PCLK_SRC_MUX_0_CLK] = &dsi0pll_pclk_src_mux.clkr.hw,
|
|
[PCLK_SRC_MUX_0_CLK] = &dsi0pll_pclk_src_mux.clkr.hw,
|
|
[PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw,
|
|
[PCLK_SRC_0_CLK] = &dsi0pll_pclk_src.clkr.hw,
|
|
[PCLK_MUX_0_CLK] = &dsi0pll_pclk_mux.clkr.hw,
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[PCLK_MUX_0_CLK] = &dsi0pll_pclk_mux.clkr.hw,
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+ [SHADOW_VCO_CLK_0] = &dsi0pll_shadow_vco_clk.hw,
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+ [SHADOW_PLL_OUT_DIV_0_CLK] = &dsi0pll_shadow_pll_out_div.clkr.hw,
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+ [SHADOW_BITCLK_SRC_0_CLK] = &dsi0pll_shadow_bitclk_src.clkr.hw,
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+ [SHADOW_BYTECLK_SRC_0_CLK] = &dsi0pll_shadow_byteclk_src.hw,
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+ [SHADOW_POST_BIT_DIV_0_CLK] = &dsi0pll_shadow_post_bit_div.hw,
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+ [SHADOW_POST_VCO_DIV_0_CLK] = &dsi0pll_shadow_post_vco_div.hw,
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+ [SHADOW_PCLK_SRC_MUX_0_CLK] = &dsi0pll_shadow_pclk_src_mux.clkr.hw,
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+ [SHADOW_PCLK_SRC_0_CLK] = &dsi0pll_shadow_pclk_src.clkr.hw,
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[VCO_CLK_1] = &dsi1pll_vco_clk.hw,
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[VCO_CLK_1] = &dsi1pll_vco_clk.hw,
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[PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw,
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[PLL_OUT_DIV_1_CLK] = &dsi1pll_pll_out_div.clkr.hw,
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[BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw,
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[BITCLK_SRC_1_CLK] = &dsi1pll_bitclk_src.clkr.hw,
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@@ -1513,6 +2058,14 @@ static struct clk_hw *mdss_dsi_pllcc_10nm[] = {
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[PCLK_SRC_MUX_1_CLK] = &dsi1pll_pclk_src_mux.clkr.hw,
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[PCLK_SRC_MUX_1_CLK] = &dsi1pll_pclk_src_mux.clkr.hw,
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[PCLK_SRC_1_CLK] = &dsi1pll_pclk_src.clkr.hw,
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[PCLK_SRC_1_CLK] = &dsi1pll_pclk_src.clkr.hw,
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[PCLK_MUX_1_CLK] = &dsi1pll_pclk_mux.clkr.hw,
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[PCLK_MUX_1_CLK] = &dsi1pll_pclk_mux.clkr.hw,
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+ [SHADOW_VCO_CLK_1] = &dsi1pll_shadow_vco_clk.hw,
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+ [SHADOW_PLL_OUT_DIV_1_CLK] = &dsi1pll_shadow_pll_out_div.clkr.hw,
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+ [SHADOW_BITCLK_SRC_1_CLK] = &dsi1pll_shadow_bitclk_src.clkr.hw,
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+ [SHADOW_BYTECLK_SRC_1_CLK] = &dsi1pll_shadow_byteclk_src.hw,
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+ [SHADOW_POST_BIT_DIV_1_CLK] = &dsi1pll_shadow_post_bit_div.hw,
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+ [SHADOW_POST_VCO_DIV_1_CLK] = &dsi1pll_shadow_post_vco_div.hw,
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+ [SHADOW_PCLK_SRC_MUX_1_CLK] = &dsi1pll_shadow_pclk_src_mux.clkr.hw,
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+ [SHADOW_PCLK_SRC_1_CLK] = &dsi1pll_shadow_pclk_src.clkr.hw,
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};
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};
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int dsi_pll_clock_register_10nm(struct platform_device *pdev,
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int dsi_pll_clock_register_10nm(struct platform_device *pdev,
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@@ -1549,18 +2102,20 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev,
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|
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/* Establish client data */
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/* Establish client data */
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if (ndx == 0) {
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if (ndx == 0) {
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-
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rmap = devm_regmap_init(&pdev->dev, &pll_regmap_bus,
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rmap = devm_regmap_init(&pdev->dev, &pll_regmap_bus,
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pll_res, &dsi_pll_10nm_config);
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pll_res, &dsi_pll_10nm_config);
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dsi0pll_pll_out_div.clkr.regmap = rmap;
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dsi0pll_pll_out_div.clkr.regmap = rmap;
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+ dsi0pll_shadow_pll_out_div.clkr.regmap = rmap;
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|
|
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rmap = devm_regmap_init(&pdev->dev, &bitclk_src_regmap_bus,
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rmap = devm_regmap_init(&pdev->dev, &bitclk_src_regmap_bus,
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pll_res, &dsi_pll_10nm_config);
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pll_res, &dsi_pll_10nm_config);
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dsi0pll_bitclk_src.clkr.regmap = rmap;
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dsi0pll_bitclk_src.clkr.regmap = rmap;
|
|
|
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+ dsi0pll_shadow_bitclk_src.clkr.regmap = rmap;
|
|
|
|
|
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rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
|
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rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
|
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pll_res, &dsi_pll_10nm_config);
|
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pll_res, &dsi_pll_10nm_config);
|
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dsi0pll_pclk_src.clkr.regmap = rmap;
|
|
dsi0pll_pclk_src.clkr.regmap = rmap;
|
|
|
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+ dsi0pll_shadow_pclk_src.clkr.regmap = rmap;
|
|
|
|
|
|
rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
|
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pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
@@ -1569,12 +2124,16 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev,
|
|
rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,
|
|
pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
dsi0pll_pclk_src_mux.clkr.regmap = rmap;
|
|
dsi0pll_pclk_src_mux.clkr.regmap = rmap;
|
|
|
|
+ dsi0pll_shadow_pclk_src_mux.clkr.regmap = rmap;
|
|
|
|
+
|
|
rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
|
|
pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
dsi0pll_byteclk_mux.clkr.regmap = rmap;
|
|
dsi0pll_byteclk_mux.clkr.regmap = rmap;
|
|
|
|
|
|
dsi0pll_vco_clk.priv = pll_res;
|
|
dsi0pll_vco_clk.priv = pll_res;
|
|
- for (i = VCO_CLK_0; i <= PCLK_MUX_0_CLK; i++) {
|
|
|
|
|
|
+ dsi0pll_shadow_vco_clk.priv = pll_res;
|
|
|
|
+
|
|
|
|
+ for (i = VCO_CLK_0; i <= SHADOW_PCLK_SRC_0_CLK; i++) {
|
|
clk = devm_clk_register(&pdev->dev,
|
|
clk = devm_clk_register(&pdev->dev,
|
|
mdss_dsi_pllcc_10nm[i]);
|
|
mdss_dsi_pllcc_10nm[i]);
|
|
if (IS_ERR(clk)) {
|
|
if (IS_ERR(clk)) {
|
|
@@ -1589,20 +2148,21 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev,
|
|
|
|
|
|
rc = of_clk_add_provider(pdev->dev.of_node,
|
|
rc = of_clk_add_provider(pdev->dev.of_node,
|
|
of_clk_src_onecell_get, clk_data);
|
|
of_clk_src_onecell_get, clk_data);
|
|
-
|
|
|
|
-
|
|
|
|
} else {
|
|
} else {
|
|
rmap = devm_regmap_init(&pdev->dev, &pll_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &pll_regmap_bus,
|
|
pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
dsi1pll_pll_out_div.clkr.regmap = rmap;
|
|
dsi1pll_pll_out_div.clkr.regmap = rmap;
|
|
|
|
+ dsi1pll_shadow_pll_out_div.clkr.regmap = rmap;
|
|
|
|
|
|
rmap = devm_regmap_init(&pdev->dev, &bitclk_src_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &bitclk_src_regmap_bus,
|
|
pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
dsi1pll_bitclk_src.clkr.regmap = rmap;
|
|
dsi1pll_bitclk_src.clkr.regmap = rmap;
|
|
|
|
+ dsi1pll_shadow_bitclk_src.clkr.regmap = rmap;
|
|
|
|
|
|
rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &pclk_src_regmap_bus,
|
|
pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
dsi1pll_pclk_src.clkr.regmap = rmap;
|
|
dsi1pll_pclk_src.clkr.regmap = rmap;
|
|
|
|
+ dsi1pll_shadow_pclk_src.clkr.regmap = rmap;
|
|
|
|
|
|
rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
|
|
pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
@@ -1611,12 +2171,16 @@ int dsi_pll_clock_register_10nm(struct platform_device *pdev,
|
|
rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &pclk_src_mux_regmap_bus,
|
|
pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
dsi1pll_pclk_src_mux.clkr.regmap = rmap;
|
|
dsi1pll_pclk_src_mux.clkr.regmap = rmap;
|
|
|
|
+ dsi1pll_shadow_pclk_src_mux.clkr.regmap = rmap;
|
|
|
|
+
|
|
rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
|
|
rmap = devm_regmap_init(&pdev->dev, &mdss_mux_regmap_bus,
|
|
pll_res, &dsi_pll_10nm_config);
|
|
pll_res, &dsi_pll_10nm_config);
|
|
dsi1pll_byteclk_mux.clkr.regmap = rmap;
|
|
dsi1pll_byteclk_mux.clkr.regmap = rmap;
|
|
|
|
+
|
|
dsi1pll_vco_clk.priv = pll_res;
|
|
dsi1pll_vco_clk.priv = pll_res;
|
|
|
|
+ dsi1pll_shadow_vco_clk.priv = pll_res;
|
|
|
|
|
|
- for (i = VCO_CLK_1; i <= PCLK_MUX_1_CLK; i++) {
|
|
|
|
|
|
+ for (i = VCO_CLK_1; i <= SHADOW_PCLK_SRC_1_CLK; i++) {
|
|
clk = devm_clk_register(&pdev->dev,
|
|
clk = devm_clk_register(&pdev->dev,
|
|
mdss_dsi_pllcc_10nm[i]);
|
|
mdss_dsi_pllcc_10nm[i]);
|
|
if (IS_ERR(clk)) {
|
|
if (IS_ERR(clk)) {
|