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disp: pll: add support for 10nm DSI PLL shadow clock

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Add support for 10nm DSI PLL shadow clocks, which will be
used during dynamic dsi clock switch and dfps feature.

Change-Id: Ib61bc5dcb5304bc1e3c7568c1419737580da3c88
Signed-off-by: Sandeep Panda <spanda@codeaurora.org>
Signed-off-by: Ritesh Kumar <riteshk@codeaurora.org>
Signed-off-by: Yujun Zhang <yujunzhang@codeaurora.org>
Signed-off-by: Ray Zhang <rayz@codeaurora.org>
This commit is contained in:
Yujun Zhang
2018-10-20 23:33:14 +05:30
parent 90ae258727
commit 01c0dad6ee
3 changed files with 607 additions and 43 deletions
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22
pll/pll_drv.h
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@@ -33,6 +33,8 @@
writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \
(base) + (offset))
#define upper_8_bit(x) ((((x) >> 2) & 0x100) >> 8)
enum {
MDSS_DSI_PLL_10NM,
MDSS_DP_PLL_10NM,
@@ -51,30 +53,23 @@ enum {
MDSS_PLL_TARGET_8996,
};
#define DFPS_MAX_NUM_OF_FRAME_RATES 20
struct dfps_panel_info {
uint32_t enabled;
uint32_t frame_rate_cnt;
uint32_t frame_rate[DFPS_MAX_NUM_OF_FRAME_RATES]; /* hz */
};
#define DFPS_MAX_NUM_OF_FRAME_RATES 16
struct dfps_pll_codes {
uint32_t pll_codes_1;
uint32_t pll_codes_2;
uint32_t pll_codes_3;
};
struct dfps_codes_info {
uint32_t is_valid;
uint32_t frame_rate; /* hz */
uint32_t clk_rate; /* hz */
struct dfps_pll_codes pll_codes;
};
struct dfps_info {
struct dfps_panel_info panel_dfps;
uint32_t vco_rate_cnt;
struct dfps_codes_info codes_dfps[DFPS_MAX_NUM_OF_FRAME_RATES];
void *dfps_fb_base;
};
struct mdss_pll_resources {
@@ -149,7 +144,7 @@ struct mdss_pll_resources {
/*
* caching the pll trim codes in the case of dynamic refresh
*/
int cache_pll_trim_codes[2];
int cache_pll_trim_codes[3];
/*
* for maintaining the status of saving trim codes
@@ -191,6 +186,11 @@ struct mdss_pll_resources {
*/
struct dfps_info *dfps;
/*
* for cases where dfps trigger happens before first
* suspend/resume and handoff is not finished.
*/
bool dfps_trigger;
};
struct mdss_pll_vco_calc {