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@@ -4573,12 +4573,44 @@ static void _sde_perf_parse_dt_cfg_populate(struct sde_mdss_cfg *cfg,
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DEFAULT_AXI_BUS_WIDTH;
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}
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+/**
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+ * _sde_set_possible_cpu_mask - checks defective cores in qos mask and update the
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+ * mask to avoid defective cores and add next possible cores for pm qos vote.
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+ * @qos_mask: qos_mask set from DT
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+ */
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+static int _sde_set_possible_cpu_mask(unsigned long qos_mask)
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+{
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+ int cpu = 0, defective_cores_count = 0;
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+ struct cpumask *cpu_qos_mask = to_cpumask(&qos_mask);
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+ unsigned long cpu_p_mask = cpu_possible_mask->bits[0];
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+ unsigned long cpu_defective_qos = qos_mask & (~cpu_p_mask);
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+
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+ /* Count all the defective cores in cpu_defective_qos */
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+ defective_cores_count = cpumask_weight(to_cpumask(&cpu_defective_qos));
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+
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+ for_each_cpu(cpu, cpu_all_mask) {
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+ if (cpu_possible(cpu) && !cpumask_test_cpu(cpu, cpu_qos_mask) &&
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+ defective_cores_count > 0) {
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+ /* Set next possible cpu */
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+ cpumask_set_cpu(cpu, cpu_qos_mask);
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+ defective_cores_count--;
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+ } else if (cpumask_test_cpu(cpu, cpu_qos_mask) && !cpu_possible(cpu)) {
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+ /* Unset the defective core from qos mask */
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+ cpumask_clear_cpu(cpu, cpu_qos_mask);
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+ }
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+ }
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+
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+ qos_mask = cpu_qos_mask->bits[0];
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+ return qos_mask;
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+}
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+
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static int _sde_perf_parse_dt_cfg(struct device_node *np,
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struct sde_mdss_cfg *cfg, int *prop_count,
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struct sde_prop_value *prop_value, bool *prop_exists)
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{
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int rc, j;
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const char *str = NULL;
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+ unsigned long qos_mask = 0;
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/*
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* The following performance parameters (e.g. core_ib_ff) are
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@@ -4622,14 +4654,16 @@ static int _sde_perf_parse_dt_cfg(struct device_node *np,
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set_bit(SDE_FEATURE_CDP, cfg->features);
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}
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- cfg->perf.cpu_mask =
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- prop_exists[PERF_CPU_MASK] ?
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+ qos_mask = prop_exists[PERF_CPU_MASK] ?
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PROP_VALUE_ACCESS(prop_value, PERF_CPU_MASK, 0) :
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DEFAULT_CPU_MASK;
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- cfg->perf.cpu_mask_perf =
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- prop_exists[CPU_MASK_PERF] ?
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+ cfg->perf.cpu_mask = _sde_set_possible_cpu_mask(qos_mask);
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+
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+ qos_mask = prop_exists[CPU_MASK_PERF] ?
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PROP_VALUE_ACCESS(prop_value, CPU_MASK_PERF, 0) :
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DEFAULT_CPU_MASK;
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+ cfg->perf.cpu_mask_perf = _sde_set_possible_cpu_mask(qos_mask);
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+
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cfg->perf.cpu_dma_latency =
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prop_exists[PERF_CPU_DMA_LATENCY] ?
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PROP_VALUE_ACCESS(prop_value, PERF_CPU_DMA_LATENCY, 0) :
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