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wsa: soundwire: Add support for 4p8MHz DAC rate

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Add support to use 4p8MHz DAC rate for receiver over WSA.

Change-Id: Ia0811670326be8131687fbdff70464da063902b2
Signed-off-by: Laxminath Kasam <lkasam@codeaurora.org>
This commit is contained in:
Laxminath Kasam
2021-03-01 19:58:10 +05:30
committed by Gerrit - the friendly Code Review server
parent ae258cb2f8
commit 001ba433b2
7 changed files with 80 additions and 8 deletions
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4
asoc/codecs/bolero/wsa-macro.c
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@@ -1714,6 +1714,8 @@ static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00); BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x00);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80); BOLERO_CDC_WSA_COMPANDER0_CTL3, 0x80, 0x80);
snd_soc_component_update_bits(component,
BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 0x08, 0x00);
} }
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
@@ -1729,6 +1731,8 @@ static int wsa_macro_config_ear_spkr_gain(struct snd_soc_component *component,
dev_dbg(wsa_priv->dev, "%s: Reset RX0 Volume to 0 dB\n", dev_dbg(wsa_priv->dev, "%s: Reset RX0 Volume to 0 dB\n",
__func__); __func__);
} }
snd_soc_component_update_bits(component,
BOLERO_CDC_WSA_RX0_RX_PATH_CFG1, 0x08, 0x08);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01); BOLERO_CDC_WSA_COMPANDER0_CTL7, 0x01, 0x01);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,

6
asoc/codecs/lpass-cdc/lpass-cdc-wsa-macro.c
View File

@@ -1587,8 +1587,14 @@ static int lpass_cdc_wsa_macro_enable_interpolator(struct snd_soc_dapm_widget *w
lpass_cdc_wsa_macro_config_compander(component, w->shift, event); lpass_cdc_wsa_macro_config_compander(component, w->shift, event);
lpass_cdc_wsa_macro_config_softclip(component, w->shift, event); lpass_cdc_wsa_macro_config_softclip(component, w->shift, event);
if(wsa_priv->wsa_spkrrecv)
snd_soc_component_update_bits(component,
LPASS_CDC_WSA_RX0_RX_PATH_CFG1,
0x08, 0x00);
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
LPASS_CDC_WSA_RX0_RX_PATH_CFG1, 0x08, 0x08);
lpass_cdc_wsa_macro_config_compander(component, w->shift, event); lpass_cdc_wsa_macro_config_compander(component, w->shift, event);
lpass_cdc_wsa_macro_config_softclip(component, w->shift, event); lpass_cdc_wsa_macro_config_softclip(component, w->shift, event);
lpass_cdc_wsa_macro_enable_prim_interpolator(component, reg, event); lpass_cdc_wsa_macro_enable_prim_interpolator(component, reg, event);

6
asoc/codecs/lpass-cdc/lpass-cdc-wsa2-macro.c
View File

@@ -1587,8 +1587,14 @@ static int lpass_cdc_wsa2_macro_enable_interpolator(struct snd_soc_dapm_widget *
lpass_cdc_wsa2_macro_config_compander(component, w->shift, event); lpass_cdc_wsa2_macro_config_compander(component, w->shift, event);
lpass_cdc_wsa2_macro_config_softclip(component, w->shift, event); lpass_cdc_wsa2_macro_config_softclip(component, w->shift, event);
if(wsa2_priv->wsa_spkrrecv)
snd_soc_component_update_bits(component,
LPASS_CDC_WSA2_RX0_RX_PATH_CFG1,
0x08, 0x00);
break; break;
case SND_SOC_DAPM_POST_PMD: case SND_SOC_DAPM_POST_PMD:
snd_soc_component_update_bits(component,
LPASS_CDC_WSA2_RX0_RX_PATH_CFG1, 0x08, 0x08);
lpass_cdc_wsa2_macro_config_compander(component, w->shift, event); lpass_cdc_wsa2_macro_config_compander(component, w->shift, event);
lpass_cdc_wsa2_macro_config_softclip(component, w->shift, event); lpass_cdc_wsa2_macro_config_softclip(component, w->shift, event);
lpass_cdc_wsa2_macro_enable_prim_interpolator(component, reg, event); lpass_cdc_wsa2_macro_enable_prim_interpolator(component, reg, event);

24
asoc/codecs/wsa883x/wsa883x.c
View File

@@ -1041,6 +1041,8 @@ static int wsa883x_enable_swr_dac_port(struct snd_soc_dapm_widget *w,
&port_id[num_port], &num_ch[num_port], &port_id[num_port], &num_ch[num_port],
&ch_mask[num_port], &ch_rate[num_port], &ch_mask[num_port], &ch_rate[num_port],
&port_type[num_port]); &port_type[num_port]);
if (wsa883x->dev_mode == RECEIVER)
ch_rate[num_port] = SWR_CLK_RATE_4P8MHZ;
++num_port; ++num_port;
if (wsa883x->comp_enable) { if (wsa883x->comp_enable) {
@@ -1113,20 +1115,32 @@ static int wsa883x_spkr_event(struct snd_soc_dapm_widget *w,
dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event); dev_dbg(component->dev, "%s: %s %d\n", __func__, w->name, event);
switch (event) { switch (event) {
case SND_SOC_DAPM_POST_PMU: case SND_SOC_DAPM_POST_PMU:
swr_slvdev_datapath_control(wsa883x->swr_slave,
wsa883x->swr_slave->dev_num,
true);
/* Added delay as per HW sequence */
usleep_range(250, 300);
if (wsa883x->dev_mode == RECEIVER) { if (wsa883x->dev_mode == RECEIVER) {
snd_soc_component_update_bits(component,
WSA883X_CDC_PATH_MODE,
0x02, 0x02);
snd_soc_component_update_bits(component,
WSA883X_SPKR_PWM_CLK_CTL,
0x08, 0x08);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
WSA883X_DRE_CTL_0, WSA883X_DRE_CTL_0,
0xF0, 0x00); 0xF0, 0x00);
} else if (wsa883x->dev_mode == SPEAKER) { } else if (wsa883x->dev_mode == SPEAKER) {
snd_soc_component_update_bits(component,
WSA883X_CDC_PATH_MODE,
0x02, 0x00);
snd_soc_component_update_bits(component,
WSA883X_SPKR_PWM_CLK_CTL,
0x08, 0x00);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
WSA883X_DRE_CTL_0, WSA883X_DRE_CTL_0,
0xF0, 0x90); 0xF0, 0x90);
} }
swr_slvdev_datapath_control(wsa883x->swr_slave,
wsa883x->swr_slave->dev_num,
true);
/* Added delay as per HW sequence */
usleep_range(250, 300);
snd_soc_component_update_bits(component, snd_soc_component_update_bits(component,
WSA883X_DRE_CTL_1, WSA883X_DRE_CTL_1,
0x01, 0x01); 0x01, 0x01);

15
asoc/lahaina-port-config.h
View File

@@ -1,6 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* /*
* Copyright (c) 2018-2020, The Linux Foundation. All rights reserved. * Copyright (c) 2018-2021, The Linux Foundation. All rights reserved.
*/ */
#ifndef _LAHAINA_PORT_CONFIG #ifndef _LAHAINA_PORT_CONFIG
@@ -27,6 +27,17 @@ static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
}; };
static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
{3, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{31, 2, 3, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
{63, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{3, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
{15, 3, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
};
static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = { static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00},
{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x00},
@@ -60,6 +71,7 @@ static struct swr_mstr_port_map sm_port_map[] = {
{RX_MACRO, SWR_UC1, rx_frame_params_dsd}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd},
{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz}, {RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
{WSA_MACRO, SWR_UC0, wsa_frame_params_default}, {WSA_MACRO, SWR_UC0, wsa_frame_params_default},
{WSA_MACRO, SWR_UC1, wsa_frame_params_receiver},
}; };
static struct swr_mstr_port_map sm_port_map_shima[] = { static struct swr_mstr_port_map sm_port_map_shima[] = {
@@ -67,6 +79,7 @@ static struct swr_mstr_port_map sm_port_map_shima[] = {
{RX_MACRO, SWR_UC1, rx_frame_params_dsd}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd},
{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz}, {RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
{WSA_MACRO, SWR_UC0, wsa_frame_params_default}, {WSA_MACRO, SWR_UC0, wsa_frame_params_default},
{WSA_MACRO, SWR_UC1, wsa_frame_params_receiver},
}; };
#endif /* _LAHAINA_PORT_CONFIG */ #endif /* _LAHAINA_PORT_CONFIG */

13
asoc/waipio-port-config.h
View File

@@ -26,6 +26,17 @@ static struct port_params wsa_frame_params_default[SWR_MSTR_PORT_LEN] = {
{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00}, {15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
}; };
static struct port_params wsa_frame_params_receiver[SWR_MSTR_PORT_LEN] = {
{3, 1, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{31, 2, 3, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
{63, 7, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{3, 6, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{31, 18, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{63, 13, 31, 0xFF, 0xFF, 0xFF, 0x1, 0xFF, 0xFF, 0x00, 0x00},
{15, 3, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
{15, 10, 0, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00},
};
static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = { static struct port_params rx_frame_params_dsd[SWR_MSTR_PORT_LEN] = {
{3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00}, {3, 0, 0, 0xFF, 0xFF, 1, 0xFF, 0xFF, 1, 0x00, 0x00},
{31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02}, {31, 0, 0, 3, 6, 7, 0, 0xFF, 0, 0x00, 0x02},
@@ -59,7 +70,9 @@ static struct swr_mstr_port_map sm_port_map[] = {
{RX_MACRO, SWR_UC1, rx_frame_params_dsd}, {RX_MACRO, SWR_UC1, rx_frame_params_dsd},
{RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz}, {RX_MACRO, SWR_UC2, rx_frame_params_44p1KHz},
{WSA_MACRO, SWR_UC0, wsa_frame_params_default}, {WSA_MACRO, SWR_UC0, wsa_frame_params_default},
{WSA_MACRO, SWR_UC1, wsa_frame_params_receiver},
{WSA2_MACRO, SWR_UC0, wsa_frame_params_default}, {WSA2_MACRO, SWR_UC0, wsa_frame_params_default},
{WSA2_MACRO, SWR_UC1, wsa_frame_params_receiver},
}; };
#endif /* _WAIPIO_PORT_CONFIG */ #endif /* _WAIPIO_PORT_CONFIG */

20
soc/swr-mstr-ctrl.c
View File

@@ -40,6 +40,8 @@
#define SWRM_DSD_PARAMS_PORT 4 #define SWRM_DSD_PARAMS_PORT 4
#define SWRM_SPK_DAC_PORT_RECEIVER 0
#define SWR_BROADCAST_CMD_ID 0x0F #define SWR_BROADCAST_CMD_ID 0x0F
#define SWR_DEV_ID_MASK 0xFFFFFFFFFFFF #define SWR_DEV_ID_MASK 0xFFFFFFFFFFFF
#define SWR_REG_VAL_PACK(data, dev, id, reg) \ #define SWR_REG_VAL_PACK(data, dev, id, reg) \
@@ -748,6 +750,12 @@ static int swrm_get_port_config(struct swr_mstr_ctrl *swrm)
(swrm->bus_clk == SWR_CLK_RATE_11P2896MHZ)) (swrm->bus_clk == SWR_CLK_RATE_11P2896MHZ))
usecase = 2; usecase = 2;
if ((swrm->master_id == MASTER_ID_WSA) &&
swrm->mport_cfg[SWRM_SPK_DAC_PORT_RECEIVER].port_en &&
swrm->mport_cfg[SWRM_SPK_DAC_PORT_RECEIVER].ch_rate ==
SWR_CLK_RATE_4P8MHZ)
usecase = 1;
params = swrm->port_param[usecase]; params = swrm->port_param[usecase];
copy_port_tables(swrm, params); copy_port_tables(swrm, params);
@@ -1522,8 +1530,7 @@ static void swrm_copy_data_port_config(struct swr_master *master, u8 bank)
port_req->dev_num, 0x00, port_req->dev_num, 0x00,
SWRS_DP_BLOCK_CONTROL_1(slv_id)); SWRS_DP_BLOCK_CONTROL_1(slv_id));
} }
if (port_req->blk_pack_mode != SWR_INVALID_PARAM if (port_req->blk_pack_mode != SWR_INVALID_PARAM) {
&& swrm->master_id != MASTER_ID_WSA) {
reg[len] = SWRM_CMD_FIFO_WR_CMD; reg[len] = SWRM_CMD_FIFO_WR_CMD;
val[len++] = val[len++] =
SWR_REG_VAL_PACK( SWR_REG_VAL_PACK(
@@ -1858,6 +1865,15 @@ static int swrm_connect_port(struct swr_master *master,
swrm->dynamic_port_map_supported) { swrm->dynamic_port_map_supported) {
mport->ch_rate += portinfo->ch_rate[i]; mport->ch_rate += portinfo->ch_rate[i];
swrm_update_bus_clk(swrm); swrm_update_bus_clk(swrm);
} else {
/*
* Fallback to assign slave port ch_rate
* as master port uses same ch_rate as slave
* unlike soundwire TX master ports where
* unified ports and multiple slave port
* channels can attach to same master port
*/
mport->ch_rate = portinfo->ch_rate[i];
} }
} }
master->num_port += portinfo->num_port; master->num_port += portinfo->num_port;