// SPDX-License-Identifier: GPL-2.0-only
/*
 * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.
 */

#include <linux/regmap.h>
#include <linux/device.h>
#include <asoc/wcd934x_registers.h>
#include "../core.h"
#include "../wcd9xxx-regmap.h"


static const struct reg_sequence wcd934x_1_1_defaults[] = {
	{ WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,             0x01 },
	{ WCD934X_BIAS_VBG_FINE_ADJ,                        0x75 },
	{ WCD934X_HPH_REFBUFF_LP_CTL,                       0x0E },
	{ WCD934X_EAR_DAC_CTL_ATEST,                        0x08 },
	{ WCD934X_SIDO_NEW_VOUT_A_STARTUP,                  0x17 },
	{ WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL,                0x40 },
	{ WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_L,               0x81 },
	{ WCD934X_HPH_NEW_INT_RDAC_HD2_CTL_R,               0x81 },
};

static const struct reg_default wcd934x_defaults[] = {
	{ WCD934X_PAGE0_PAGE_REGISTER,                      0x00 },
	{ WCD934X_CODEC_RPM_CLK_BYPASS,                     0x00 },
	{ WCD934X_CODEC_RPM_CLK_GATE,                       0x1f },
	{ WCD934X_CODEC_RPM_CLK_MCLK_CFG,                   0x00 },
	{ WCD934X_CODEC_RPM_CLK_MCLK2_CFG,                  0x02 },
	{ WCD934X_CODEC_RPM_I2S_DSD_CLK_SEL,                0x00 },
	{ WCD934X_CODEC_RPM_RST_CTL,                        0x00 },
	{ WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL,             0x04 },
	{ WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE0,             0x00 },
	{ WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE1,             0x00 },
	{ WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE2,             0x08 },
	{ WCD934X_CHIP_TIER_CTRL_CHIP_ID_BYTE3,             0x01 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_CTL,                 0x10 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_TEST0,               0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_TEST1,               0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT0,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT1,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT2,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT3,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT4,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT5,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT6,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT7,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT8,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT9,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT10,           0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT11,           0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT12,           0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT13,           0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT14,           0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_VAL_OUT15,           0x00 },
	{ WCD934X_CHIP_TIER_CTRL_EFUSE_STATUS,              0x00 },
	{ WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_NONNEGO,      0x0d },
	{ WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_1,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_2,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_I2C_SLAVE_ID_3,            0x00 },
	{ WCD934X_CHIP_TIER_CTRL_ANA_WAIT_STATE_CTL,        0xcc },
	{ WCD934X_CHIP_TIER_CTRL_SLNQ_WAIT_STATE_CTL,       0xcc },
	{ WCD934X_CHIP_TIER_CTRL_I2C_ACTIVE,                0x00 },
	{ WCD934X_CHIP_TIER_CTRL_ALT_FUNC_EN,               0x00 },
	{ WCD934X_CHIP_TIER_CTRL_GPIO_CTL_OE,               0x00 },
	{ WCD934X_CHIP_TIER_CTRL_GPIO_CTL_DATA,             0x00 },
	{ WCD934X_DATA_HUB_RX0_CFG,                         0x00 },
	{ WCD934X_DATA_HUB_RX1_CFG,                         0x00 },
	{ WCD934X_DATA_HUB_RX2_CFG,                         0x00 },
	{ WCD934X_DATA_HUB_RX3_CFG,                         0x00 },
	{ WCD934X_DATA_HUB_RX4_CFG,                         0x00 },
	{ WCD934X_DATA_HUB_RX5_CFG,                         0x00 },
	{ WCD934X_DATA_HUB_RX6_CFG,                         0x00 },
	{ WCD934X_DATA_HUB_RX7_CFG,                         0x00 },
	{ WCD934X_DATA_HUB_SB_TX0_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX1_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX2_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX3_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX4_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX5_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX6_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX7_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX8_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX9_INP_CFG,                  0x00 },
	{ WCD934X_DATA_HUB_SB_TX10_INP_CFG,                 0x00 },
	{ WCD934X_DATA_HUB_SB_TX11_INP_CFG,                 0x00 },
	{ WCD934X_DATA_HUB_SB_TX13_INP_CFG,                 0x00 },
	{ WCD934X_DATA_HUB_SB_TX14_INP_CFG,                 0x00 },
	{ WCD934X_DATA_HUB_SB_TX15_INP_CFG,                 0x00 },
	{ WCD934X_DATA_HUB_I2S_TX0_CFG,                     0x00 },
	{ WCD934X_DATA_HUB_I2S_TX1_0_CFG,                   0x00 },
	{ WCD934X_DATA_HUB_I2S_TX1_1_CFG,                   0x00 },
	{ WCD934X_DATA_HUB_I2S_0_CTL,                       0x0c },
	{ WCD934X_DATA_HUB_I2S_1_CTL,                       0x0c },
	{ WCD934X_DATA_HUB_I2S_2_CTL,                       0x0c },
	{ WCD934X_DATA_HUB_I2S_3_CTL,                       0x0c },
	{ WCD934X_DATA_HUB_I2S_CLKSRC_CTL,                  0x00 },
	{ WCD934X_DATA_HUB_I2S_COMMON_CTL,                  0x00 },
	{ WCD934X_DATA_HUB_I2S_0_TDM_CTL,                   0x00 },
	{ WCD934X_DATA_HUB_I2S_STATUS,                      0x00 },
	{ WCD934X_DMA_RDMA_CTL_0,                           0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_RDMA_0,                    0xff },
	{ WCD934X_DMA_CH_0_1_CFG_RDMA_0,                    0xff },
	{ WCD934X_DMA_RDMA_CTL_1,                           0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_RDMA_1,                    0xff },
	{ WCD934X_DMA_CH_0_1_CFG_RDMA_1,                    0xff },
	{ WCD934X_DMA_RDMA_CTL_2,                           0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_RDMA_2,                    0xff },
	{ WCD934X_DMA_CH_0_1_CFG_RDMA_2,                    0xff },
	{ WCD934X_DMA_RDMA_CTL_3,                           0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_RDMA_3,                    0xff },
	{ WCD934X_DMA_CH_0_1_CFG_RDMA_3,                    0xff },
	{ WCD934X_DMA_RDMA_CTL_4,                           0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_RDMA_4,                    0xff },
	{ WCD934X_DMA_CH_0_1_CFG_RDMA_4,                    0xff },
	{ WCD934X_DMA_RDMA4_PRT_CFG,                       0x00 },
	{ WCD934X_DMA_RDMA_SBTX0_7_CFG,                    0x00 },
	{ WCD934X_DMA_RDMA_SBTX8_11_CFG,                   0x00 },
	{ WCD934X_DMA_WDMA_CTL_0,                          0x00 },
	{ WCD934X_DMA_CH_4_5_CFG_WDMA_0,                   0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_WDMA_0,                   0x00 },
	{ WCD934X_DMA_CH_0_1_CFG_WDMA_0,                   0x00 },
	{ WCD934X_DMA_WDMA_CTL_1,                          0x00 },
	{ WCD934X_DMA_CH_4_5_CFG_WDMA_1,                   0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_WDMA_1,                   0x00 },
	{ WCD934X_DMA_CH_0_1_CFG_WDMA_1,                   0x00 },
	{ WCD934X_DMA_WDMA_CTL_2,                          0x00 },
	{ WCD934X_DMA_CH_4_5_CFG_WDMA_2,                   0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_WDMA_2,                   0x00 },
	{ WCD934X_DMA_CH_0_1_CFG_WDMA_2,                   0x00 },
	{ WCD934X_DMA_WDMA_CTL_3,                          0x00 },
	{ WCD934X_DMA_CH_4_5_CFG_WDMA_3,                   0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_WDMA_3,                   0x00 },
	{ WCD934X_DMA_CH_0_1_CFG_WDMA_3,                   0x00 },
	{ WCD934X_DMA_WDMA_CTL_4,                          0x00 },
	{ WCD934X_DMA_CH_4_5_CFG_WDMA_4,                   0x00 },
	{ WCD934X_DMA_CH_2_3_CFG_WDMA_4,                   0x00 },
	{ WCD934X_DMA_CH_0_1_CFG_WDMA_4,                   0x00 },
	{ WCD934X_DMA_WDMA0_PRT_CFG,                       0x00 },
	{ WCD934X_DMA_WDMA3_PRT_CFG,                       0x00 },
	{ WCD934X_DMA_WDMA4_PRT0_3_CFG,                    0x00 },
	{ WCD934X_DMA_WDMA4_PRT4_7_CFG,                    0x00 },
	{ WCD934X_PAGE1_PAGE_REGISTER,                     0x00 },
	{ WCD934X_CPE_FLL_USER_CTL_0,                      0x71 },
	{ WCD934X_CPE_FLL_USER_CTL_1,                      0x34 },
	{ WCD934X_CPE_FLL_USER_CTL_2,                      0x0b },
	{ WCD934X_CPE_FLL_USER_CTL_3,                      0x02 },
	{ WCD934X_CPE_FLL_USER_CTL_4,                      0x04 },
	{ WCD934X_CPE_FLL_USER_CTL_5,                      0x02 },
	{ WCD934X_CPE_FLL_USER_CTL_6,                      0x6e },
	{ WCD934X_CPE_FLL_USER_CTL_7,                      0x00 },
	{ WCD934X_CPE_FLL_USER_CTL_8,                      0x94 },
	{ WCD934X_CPE_FLL_USER_CTL_9,                      0x50 },
	{ WCD934X_CPE_FLL_L_VAL_CTL_0,                     0x53 },
	{ WCD934X_CPE_FLL_L_VAL_CTL_1,                     0x00 },
	{ WCD934X_CPE_FLL_DSM_FRAC_CTL_0,                  0x00 },
	{ WCD934X_CPE_FLL_DSM_FRAC_CTL_1,                  0xff },
	{ WCD934X_CPE_FLL_CONFIG_CTL_0,                    0x6b },
	{ WCD934X_CPE_FLL_CONFIG_CTL_1,                    0x05 },
	{ WCD934X_CPE_FLL_CONFIG_CTL_2,                    0x08 },
	{ WCD934X_CPE_FLL_CONFIG_CTL_3,                    0x00 },
	{ WCD934X_CPE_FLL_CONFIG_CTL_4,                    0x10 },
	{ WCD934X_CPE_FLL_TEST_CTL_0,                      0x80 },
	{ WCD934X_CPE_FLL_TEST_CTL_1,                      0x00 },
	{ WCD934X_CPE_FLL_TEST_CTL_2,                      0x00 },
	{ WCD934X_CPE_FLL_TEST_CTL_3,                      0x00 },
	{ WCD934X_CPE_FLL_TEST_CTL_4,                      0x00 },
	{ WCD934X_CPE_FLL_TEST_CTL_5,                      0x00 },
	{ WCD934X_CPE_FLL_TEST_CTL_6,                      0x00 },
	{ WCD934X_CPE_FLL_TEST_CTL_7,                      0x33 },
	{ WCD934X_CPE_FLL_FREQ_CTL_0,                      0x00 },
	{ WCD934X_CPE_FLL_FREQ_CTL_1,                      0x00 },
	{ WCD934X_CPE_FLL_FREQ_CTL_2,                      0x00 },
	{ WCD934X_CPE_FLL_FREQ_CTL_3,                      0x00 },
	{ WCD934X_CPE_FLL_SSC_CTL_0,                       0x00 },
	{ WCD934X_CPE_FLL_SSC_CTL_1,                       0x00 },
	{ WCD934X_CPE_FLL_SSC_CTL_2,                       0x00 },
	{ WCD934X_CPE_FLL_SSC_CTL_3,                       0x00 },
	{ WCD934X_CPE_FLL_FLL_MODE,                        0x20 },
	{ WCD934X_CPE_FLL_STATUS_0,                        0x00 },
	{ WCD934X_CPE_FLL_STATUS_1,                        0x00 },
	{ WCD934X_CPE_FLL_STATUS_2,                        0x00 },
	{ WCD934X_CPE_FLL_STATUS_3,                        0x00 },
	{ WCD934X_I2S_FLL_USER_CTL_0,                      0x41 },
	{ WCD934X_I2S_FLL_USER_CTL_1,                      0x94 },
	{ WCD934X_I2S_FLL_USER_CTL_2,                      0x08 },
	{ WCD934X_I2S_FLL_USER_CTL_3,                      0x02 },
	{ WCD934X_I2S_FLL_USER_CTL_4,                      0x04 },
	{ WCD934X_I2S_FLL_USER_CTL_5,                      0x02 },
	{ WCD934X_I2S_FLL_USER_CTL_6,                      0x40 },
	{ WCD934X_I2S_FLL_USER_CTL_7,                      0x00 },
	{ WCD934X_I2S_FLL_USER_CTL_8,                      0x5f },
	{ WCD934X_I2S_FLL_USER_CTL_9,                      0x02 },
	{ WCD934X_I2S_FLL_L_VAL_CTL_0,                     0x40 },
	{ WCD934X_I2S_FLL_L_VAL_CTL_1,                     0x00 },
	{ WCD934X_I2S_FLL_DSM_FRAC_CTL_0,                  0x00 },
	{ WCD934X_I2S_FLL_DSM_FRAC_CTL_1,                  0xff },
	{ WCD934X_I2S_FLL_CONFIG_CTL_0,                    0x6b },
	{ WCD934X_I2S_FLL_CONFIG_CTL_1,                    0x05 },
	{ WCD934X_I2S_FLL_CONFIG_CTL_2,                    0x08 },
	{ WCD934X_I2S_FLL_CONFIG_CTL_3,                    0x00 },
	{ WCD934X_I2S_FLL_CONFIG_CTL_4,                    0x30 },
	{ WCD934X_I2S_FLL_TEST_CTL_0,                      0x80 },
	{ WCD934X_I2S_FLL_TEST_CTL_1,                      0x00 },
	{ WCD934X_I2S_FLL_TEST_CTL_2,                      0x00 },
	{ WCD934X_I2S_FLL_TEST_CTL_3,                      0x00 },
	{ WCD934X_I2S_FLL_TEST_CTL_4,                      0x00 },
	{ WCD934X_I2S_FLL_TEST_CTL_5,                      0x00 },
	{ WCD934X_I2S_FLL_TEST_CTL_6,                      0x00 },
	{ WCD934X_I2S_FLL_TEST_CTL_7,                      0xff },
	{ WCD934X_I2S_FLL_FREQ_CTL_0,                      0x00 },
	{ WCD934X_I2S_FLL_FREQ_CTL_1,                      0x00 },
	{ WCD934X_I2S_FLL_FREQ_CTL_2,                      0x00 },
	{ WCD934X_I2S_FLL_FREQ_CTL_3,                      0x00 },
	{ WCD934X_I2S_FLL_SSC_CTL_0,                       0x00 },
	{ WCD934X_I2S_FLL_SSC_CTL_1,                       0x00 },
	{ WCD934X_I2S_FLL_SSC_CTL_2,                       0x00 },
	{ WCD934X_I2S_FLL_SSC_CTL_3,                       0x00 },
	{ WCD934X_I2S_FLL_FLL_MODE,                        0x00 },
	{ WCD934X_I2S_FLL_STATUS_0,                        0x00 },
	{ WCD934X_I2S_FLL_STATUS_1,                        0x00 },
	{ WCD934X_I2S_FLL_STATUS_2,                        0x00 },
	{ WCD934X_I2S_FLL_STATUS_3,                        0x00 },
	{ WCD934X_SB_FLL_USER_CTL_0,                       0x41 },
	{ WCD934X_SB_FLL_USER_CTL_1,                       0x94 },
	{ WCD934X_SB_FLL_USER_CTL_2,                       0x08 },
	{ WCD934X_SB_FLL_USER_CTL_3,                       0x02 },
	{ WCD934X_SB_FLL_USER_CTL_4,                       0x04 },
	{ WCD934X_SB_FLL_USER_CTL_5,                       0x02 },
	{ WCD934X_SB_FLL_USER_CTL_6,                       0x40 },
	{ WCD934X_SB_FLL_USER_CTL_7,                       0x00 },
	{ WCD934X_SB_FLL_USER_CTL_8,                       0x5e },
	{ WCD934X_SB_FLL_USER_CTL_9,                       0x01 },
	{ WCD934X_SB_FLL_L_VAL_CTL_0,                      0x40 },
	{ WCD934X_SB_FLL_L_VAL_CTL_1,                      0x00 },
	{ WCD934X_SB_FLL_DSM_FRAC_CTL_0,                   0x00 },
	{ WCD934X_SB_FLL_DSM_FRAC_CTL_1,                   0xff },
	{ WCD934X_SB_FLL_CONFIG_CTL_0,                     0x6b },
	{ WCD934X_SB_FLL_CONFIG_CTL_1,                     0x05 },
	{ WCD934X_SB_FLL_CONFIG_CTL_2,                     0x08 },
	{ WCD934X_SB_FLL_CONFIG_CTL_3,                     0x00 },
	{ WCD934X_SB_FLL_CONFIG_CTL_4,                     0x10 },
	{ WCD934X_SB_FLL_TEST_CTL_0,                       0x00 },
	{ WCD934X_SB_FLL_TEST_CTL_1,                       0x00 },
	{ WCD934X_SB_FLL_TEST_CTL_2,                       0x00 },
	{ WCD934X_SB_FLL_TEST_CTL_3,                       0x00 },
	{ WCD934X_SB_FLL_TEST_CTL_4,                       0x00 },
	{ WCD934X_SB_FLL_TEST_CTL_5,                       0x00 },
	{ WCD934X_SB_FLL_TEST_CTL_6,                       0x00 },
	{ WCD934X_SB_FLL_TEST_CTL_7,                       0xff },
	{ WCD934X_SB_FLL_FREQ_CTL_0,                       0x00 },
	{ WCD934X_SB_FLL_FREQ_CTL_1,                       0x00 },
	{ WCD934X_SB_FLL_FREQ_CTL_2,                       0x00 },
	{ WCD934X_SB_FLL_FREQ_CTL_3,                       0x00 },
	{ WCD934X_SB_FLL_SSC_CTL_0,                        0x00 },
	{ WCD934X_SB_FLL_SSC_CTL_1,                        0x00 },
	{ WCD934X_SB_FLL_SSC_CTL_2,                        0x00 },
	{ WCD934X_SB_FLL_SSC_CTL_3,                        0x00 },
	{ WCD934X_SB_FLL_FLL_MODE,                         0x00 },
	{ WCD934X_SB_FLL_STATUS_0,                         0x00 },
	{ WCD934X_SB_FLL_STATUS_1,                         0x00 },
	{ WCD934X_SB_FLL_STATUS_2,                         0x00 },
	{ WCD934X_SB_FLL_STATUS_3,                         0x00 },
	{ WCD934X_PAGE2_PAGE_REGISTER,                     0x00 },
	{ WCD934X_CPE_SS_CPE_CTL,                          0x05 },
	{ WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_0,             0x01 },
	{ WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_1,             0x00 },
	{ WCD934X_CPE_SS_PWR_CPEFLL_CTL,                   0x02 },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_0,         0xff },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_1,         0x0f },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_DEEPSLP_OVERRIDE,  0x00 },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_0,        0xff },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_1,        0xff },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_2,        0xff },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_3,        0xff },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_4,        0xff },
	{ WCD934X_CPE_SS_PWR_CPE_SYSMEM_SHUTDOWN_5,        0xff },
	{ WCD934X_CPE_SS_PWR_CPE_DRAM1_SHUTDOWN,           0x07 },
	{ WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL,              0x00 },
	{ WCD934X_CPE_SS_SOC_SW_COLLAPSE_OVERRIDE_CTL,     0x20 },
	{ WCD934X_CPE_SS_SOC_SW_COLLAPSE_OVERRIDE_CTL1,    0x00 },
	{ WCD934X_CPE_SS_US_BUF_INT_PERIOD,                0x60 },
	{ WCD934X_CPE_SS_CPARMAD_BUFRDY_INT_PERIOD,        0x13 },
	{ WCD934X_CPE_SS_SVA_CFG,                          0x41 },
	{ WCD934X_CPE_SS_US_CFG,                           0x00 },
	{ WCD934X_CPE_SS_MAD_CTL,                          0x00 },
	{ WCD934X_CPE_SS_CPAR_CTL,                         0x00 },
	{ WCD934X_CPE_SS_DMIC0_CTL,                        0x00 },
	{ WCD934X_CPE_SS_DMIC1_CTL,                        0x00 },
	{ WCD934X_CPE_SS_DMIC2_CTL,                        0x00 },
	{ WCD934X_CPE_SS_DMIC_CFG,                         0x80 },
	{ WCD934X_CPE_SS_CPAR_CFG,                         0x00 },
	{ WCD934X_CPE_SS_WDOG_CFG,                         0x01 },
	{ WCD934X_CPE_SS_BACKUP_INT,                       0x00 },
	{ WCD934X_CPE_SS_STATUS,                           0x00 },
	{ WCD934X_CPE_SS_CPE_OCD_CFG,                      0x00 },
	{ WCD934X_CPE_SS_SS_ERROR_INT_MASK_0A,             0xff },
	{ WCD934X_CPE_SS_SS_ERROR_INT_MASK_0B,             0x3f },
	{ WCD934X_CPE_SS_SS_ERROR_INT_MASK_1A,             0xff },
	{ WCD934X_CPE_SS_SS_ERROR_INT_MASK_1B,             0x3f },
	{ WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0A,           0x00 },
	{ WCD934X_CPE_SS_SS_ERROR_INT_STATUS_0B,           0x00 },
	{ WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1A,           0x00 },
	{ WCD934X_CPE_SS_SS_ERROR_INT_STATUS_1B,           0x00 },
	{ WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0A,            0x00 },
	{ WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_0B,            0x00 },
	{ WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_1A,            0x00 },
	{ WCD934X_CPE_SS_SS_ERROR_INT_CLEAR_1B,            0x00 },
	{ WCD934X_SOC_MAD_MAIN_CTL_1,                      0x00 },
	{ WCD934X_SOC_MAD_MAIN_CTL_2,                      0x00 },
	{ WCD934X_SOC_MAD_AUDIO_CTL_1,                     0x00 },
	{ WCD934X_SOC_MAD_AUDIO_CTL_2,                     0x00 },
	{ WCD934X_SOC_MAD_AUDIO_CTL_3,                     0x00 },
	{ WCD934X_SOC_MAD_AUDIO_CTL_4,                     0x00 },
	{ WCD934X_SOC_MAD_AUDIO_CTL_5,                     0x00 },
	{ WCD934X_SOC_MAD_AUDIO_CTL_6,                     0x00 },
	{ WCD934X_SOC_MAD_AUDIO_CTL_7,                     0x00 },
	{ WCD934X_SOC_MAD_AUDIO_CTL_8,                     0x00 },
	{ WCD934X_SOC_MAD_AUDIO_IIR_CTL_PTR,               0x00 },
	{ WCD934X_SOC_MAD_AUDIO_IIR_CTL_VAL,               0x40 },
	{ WCD934X_SOC_MAD_ULTR_CTL_1,                      0x00 },
	{ WCD934X_SOC_MAD_ULTR_CTL_2,                      0x00 },
	{ WCD934X_SOC_MAD_ULTR_CTL_3,                      0x00 },
	{ WCD934X_SOC_MAD_ULTR_CTL_4,                      0x00 },
	{ WCD934X_SOC_MAD_ULTR_CTL_5,                      0x00 },
	{ WCD934X_SOC_MAD_ULTR_CTL_6,                      0x00 },
	{ WCD934X_SOC_MAD_ULTR_CTL_7,                      0x00 },
	{ WCD934X_SOC_MAD_BEACON_CTL_1,                    0x00 },
	{ WCD934X_SOC_MAD_BEACON_CTL_2,                    0x00 },
	{ WCD934X_SOC_MAD_BEACON_CTL_3,                    0x00 },
	{ WCD934X_SOC_MAD_BEACON_CTL_4,                    0x00 },
	{ WCD934X_SOC_MAD_BEACON_CTL_5,                    0x00 },
	{ WCD934X_SOC_MAD_BEACON_CTL_6,                    0x00 },
	{ WCD934X_SOC_MAD_BEACON_CTL_7,                    0x00 },
	{ WCD934X_SOC_MAD_BEACON_CTL_8,                    0x00 },
	{ WCD934X_SOC_MAD_BEACON_IIR_CTL_PTR,              0x00 },
	{ WCD934X_SOC_MAD_BEACON_IIR_CTL_VAL,              0x00 },
	{ WCD934X_SOC_MAD_INP_SEL,                         0x00 },
	{ WCD934X_PAGE4_PAGE_REGISTER,                     0x00 },
	{ WCD934X_INTR_CFG,                                0x00 },
	{ WCD934X_INTR_CLR_COMMIT,                         0x00 },
	{ WCD934X_INTR_PIN1_MASK0,                         0xff },
	{ WCD934X_INTR_PIN1_MASK1,                         0xff },
	{ WCD934X_INTR_PIN1_MASK2,                         0xff },
	{ WCD934X_INTR_PIN1_MASK3,                         0xff },
	{ WCD934X_INTR_PIN1_STATUS0,                       0x00 },
	{ WCD934X_INTR_PIN1_STATUS1,                       0x00 },
	{ WCD934X_INTR_PIN1_STATUS2,                       0x00 },
	{ WCD934X_INTR_PIN1_STATUS3,                       0x00 },
	{ WCD934X_INTR_PIN1_CLEAR0,                        0x00 },
	{ WCD934X_INTR_PIN1_CLEAR1,                        0x00 },
	{ WCD934X_INTR_PIN1_CLEAR2,                        0x00 },
	{ WCD934X_INTR_PIN1_CLEAR3,                        0x00 },
	{ WCD934X_INTR_PIN2_MASK3,                         0xff },
	{ WCD934X_INTR_PIN2_STATUS3,                       0x00 },
	{ WCD934X_INTR_PIN2_CLEAR3,                        0x00 },
	{ WCD934X_INTR_CPESS_SUMRY_MASK2,                  0xff },
	{ WCD934X_INTR_CPESS_SUMRY_MASK3,                  0xff },
	{ WCD934X_INTR_CPESS_SUMRY_STATUS2,                0x00 },
	{ WCD934X_INTR_CPESS_SUMRY_STATUS3,                0x00 },
	{ WCD934X_INTR_CPESS_SUMRY_CLEAR2,                 0x00 },
	{ WCD934X_INTR_CPESS_SUMRY_CLEAR3,                 0x00 },
	{ WCD934X_INTR_LEVEL0,                             0x03 },
	{ WCD934X_INTR_LEVEL1,                             0xe0 },
	{ WCD934X_INTR_LEVEL2,                             0x94 },
	{ WCD934X_INTR_LEVEL3,                             0x80 },
	{ WCD934X_INTR_BYPASS0,                            0x00 },
	{ WCD934X_INTR_BYPASS1,                            0x00 },
	{ WCD934X_INTR_BYPASS2,                            0x00 },
	{ WCD934X_INTR_BYPASS3,                            0x00 },
	{ WCD934X_INTR_SET0,                               0x00 },
	{ WCD934X_INTR_SET1,                               0x00 },
	{ WCD934X_INTR_SET2,                               0x00 },
	{ WCD934X_INTR_SET3,                               0x00 },
	{ WCD934X_INTR_CODEC_MISC_MASK,                    0x7f },
	{ WCD934X_INTR_CODEC_MISC_STATUS,                  0x00 },
	{ WCD934X_INTR_CODEC_MISC_CLEAR,                   0x00 },
	{ WCD934X_PAGE5_PAGE_REGISTER,                     0x00 },
	{ WCD934X_SLNQ_DIG_DEVICE,                         0x49 },
	{ WCD934X_SLNQ_DIG_REVISION,                       0x01 },
	{ WCD934X_SLNQ_DIG_H_COMMAND,                      0x00 },
	{ WCD934X_SLNQ_DIG_NUMBER_OF_BYTE_MSB,             0x00 },
	{ WCD934X_SLNQ_DIG_NUMBER_OF_BYTE_LSB,             0x00 },
	{ WCD934X_SLNQ_DIG_MASTER_ADDRESS_MSB,             0x00 },
	{ WCD934X_SLNQ_DIG_MASTER_ADDRESS_LSB,             0x00 },
	{ WCD934X_SLNQ_DIG_SLAVE_ADDRESS_MSB,              0x00 },
	{ WCD934X_SLNQ_DIG_SLAVE_ADDRESS_LSB,              0x00 },
	{ WCD934X_SLNQ_DIG_TIMER0_INTERRUPT_MSB,           0x40 },
	{ WCD934X_SLNQ_DIG_TIMER0_INTERRUPT_LSB,           0x00 },
	{ WCD934X_SLNQ_DIG_TIMER1_INTERRUPT_MSB,           0x40 },
	{ WCD934X_SLNQ_DIG_TIMER1_INTERRUPT_LSB,           0x00 },
	{ WCD934X_SLNQ_DIG_TIMER2_INTERRUPT_MSB,           0x40 },
	{ WCD934X_SLNQ_DIG_TIMER2_INTERRUPT_LSB,           0x00 },
	{ WCD934X_SLNQ_DIG_COMM_CTL,                       0x00 },
	{ WCD934X_SLNQ_DIG_FRAME_CTRL,                     0x01 },
	{ WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH1_2,             0x77 },
	{ WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH3_4,             0x77 },
	{ WCD934X_SLNQ_DIG_PDM_2ND_DATA_CH5,               0x70 },
	{ WCD934X_SLNQ_DIG_SW_EVENT_RD,                    0x00 },
	{ WCD934X_SLNQ_DIG_SW_EVENT_CTRL,                  0x00 },
	{ WCD934X_SLNQ_DIG_PDM_SELECT_1,                   0x12 },
	{ WCD934X_SLNQ_DIG_PDM_SELECT_2,                   0x34 },
	{ WCD934X_SLNQ_DIG_PDM_SELECT_3,                   0x55 },
	{ WCD934X_SLNQ_DIG_PDM_SAMPLING_FREQ,              0x01 },
	{ WCD934X_SLNQ_DIG_PDM_DC_CONVERSION_CTL,          0x00 },
	{ WCD934X_SLNQ_DIG_PDM_DC_CONVERSION_SEL,          0x11 },
	{ WCD934X_SLNQ_DIG_PDM_DC_CONV_CHA_MSB,            0x00 },
	{ WCD934X_SLNQ_DIG_PDM_DC_CONV_CHA_LSB,            0x00 },
	{ WCD934X_SLNQ_DIG_PDM_DC_CONV_CHB_MSB,            0x00 },
	{ WCD934X_SLNQ_DIG_PDM_DC_CONV_CHB_LSB,            0x00 },
	{ WCD934X_SLNQ_DIG_RAM_CNTRL,                      0x01 },
	{ WCD934X_SLNQ_DIG_SRAM_BANK,                      0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_0,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_1,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_2,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_3,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_4,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_5,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_6,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_7,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_8,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_9,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_A,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_B,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_C,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_D,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_E,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_F,                    0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_10,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_11,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_12,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_13,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_14,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_15,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_16,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_17,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_18,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_19,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_1A,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_1B,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_1C,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_1D,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_1E,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_1F,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_20,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_21,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_22,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_23,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_24,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_25,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_26,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_27,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_28,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_29,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_2A,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_2B,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_2C,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_2D,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_2E,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_2F,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_30,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_31,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_32,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_33,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_34,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_35,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_36,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_37,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_38,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_39,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_3A,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_3B,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_3C,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_3D,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_3E,                   0x00 },
	{ WCD934X_SLNQ_DIG_SRAM_BYTE_3F,                   0x00 },
	{ WCD934X_SLNQ_DIG_TOP_CTRL1,                      0x00 },
	{ WCD934X_SLNQ_DIG_TOP_CTRL2,                      0x00 },
	{ WCD934X_SLNQ_DIG_PDM_CTRL,                       0x00 },
	{ WCD934X_SLNQ_DIG_PDM_MUTE_CTRL,                  0x20 },
	{ WCD934X_SLNQ_DIG_DEC_BYPASS_CTRL,                0x00 },
	{ WCD934X_SLNQ_DIG_DEC_BYPASS_STATUS,              0x00 },
	{ WCD934X_SLNQ_DIG_DEC_BYPASS_FS,                  0x00 },
	{ WCD934X_SLNQ_DIG_DEC_BYPASS_IN_SEL,              0x00 },
	{ WCD934X_SLNQ_DIG_GPOUT_ENABLE,                   0x00 },
	{ WCD934X_SLNQ_DIG_GPOUT_VAL,                      0x00 },
	{ WCD934X_SLNQ_DIG_ANA_INTERRUPT_MASK,             0x00 },
	{ WCD934X_SLNQ_DIG_ANA_INTERRUPT_STATUS,           0x00 },
	{ WCD934X_SLNQ_DIG_ANA_INTERRUPT_CLR,              0x00 },
	{ WCD934X_SLNQ_DIG_IP_TESTING,                     0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CNTRL,                0x0f },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CNT,                  0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CNT_MSB,              0xff },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CNT_LSB,              0xff },
	{ WCD934X_SLNQ_DIG_INTERRUPT_MASK0,                0xff },
	{ WCD934X_SLNQ_DIG_INTERRUPT_MASK1,                0xff },
	{ WCD934X_SLNQ_DIG_INTERRUPT_MASK2,                0xff },
	{ WCD934X_SLNQ_DIG_INTERRUPT_MASK3,                0xff },
	{ WCD934X_SLNQ_DIG_INTERRUPT_MASK4,                0x1f },
	{ WCD934X_SLNQ_DIG_INTERRUPT_STATUS0,              0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_STATUS1,              0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_STATUS2,              0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_STATUS3,              0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_STATUS4,              0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CLR0,                 0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CLR1,                 0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CLR2,                 0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CLR3,                 0x00 },
	{ WCD934X_SLNQ_DIG_INTERRUPT_CLR4,                 0x00 },
	{ WCD934X_ANA_PAGE_REGISTER,                       0x00 },
	{ WCD934X_ANA_BIAS,                                0x00 },
	{ WCD934X_ANA_RCO,                                 0x00 },
	{ WCD934X_ANA_PAGE6_SPARE2,                        0x00 },
	{ WCD934X_ANA_PAGE6_SPARE3,                        0x00 },
	{ WCD934X_ANA_BUCK_CTL,                            0x00 },
	{ WCD934X_ANA_BUCK_STATUS,                         0x00 },
	{ WCD934X_ANA_RX_SUPPLIES,                         0x00 },
	{ WCD934X_ANA_HPH,                                 0x0c },
	{ WCD934X_ANA_EAR,                                 0x00 },
	{ WCD934X_ANA_LO_1_2,                              0x3c },
	{ WCD934X_ANA_MAD_SETUP,                           0x01 },
	{ WCD934X_ANA_AMIC1,                               0x20 },
	{ WCD934X_ANA_AMIC2,                               0x00 },
	{ WCD934X_ANA_AMIC3,                               0x20 },
	{ WCD934X_ANA_AMIC4,                               0x00 },
	{ WCD934X_ANA_MBHC_MECH,                           0x39 },
	{ WCD934X_ANA_MBHC_ELECT,                          0x08 },
	{ WCD934X_ANA_MBHC_ZDET,                           0x00 },
	{ WCD934X_ANA_MBHC_RESULT_1,                       0x00 },
	{ WCD934X_ANA_MBHC_RESULT_2,                       0x00 },
	{ WCD934X_ANA_MBHC_RESULT_3,                       0x00 },
	{ WCD934X_ANA_MBHC_BTN0,                           0x00 },
	{ WCD934X_ANA_MBHC_BTN1,                           0x10 },
	{ WCD934X_ANA_MBHC_BTN2,                           0x20 },
	{ WCD934X_ANA_MBHC_BTN3,                           0x30 },
	{ WCD934X_ANA_MBHC_BTN4,                           0x40 },
	{ WCD934X_ANA_MBHC_BTN5,                           0x50 },
	{ WCD934X_ANA_MBHC_BTN6,                           0x60 },
	{ WCD934X_ANA_MBHC_BTN7,                           0x70 },
	{ WCD934X_ANA_MICB1,                               0x10 },
	{ WCD934X_ANA_MICB2,                               0x10 },
	{ WCD934X_ANA_MICB2_RAMP,                          0x00 },
	{ WCD934X_ANA_MICB3,                               0x10 },
	{ WCD934X_ANA_MICB4,                               0x10 },
	{ WCD934X_ANA_VBADC,                               0x00 },
	{ WCD934X_BIAS_CTL,                                0x28 },
	{ WCD934X_BIAS_VBG_FINE_ADJ,                       0x65 },
	{ WCD934X_RCO_CTRL_1,                              0x44 },
	{ WCD934X_RCO_CTRL_2,                              0x48 },
	{ WCD934X_RCO_CAL,                                 0x00 },
	{ WCD934X_RCO_CAL_1,                               0x00 },
	{ WCD934X_RCO_CAL_2,                               0x00 },
	{ WCD934X_RCO_TEST_CTRL,                           0x00 },
	{ WCD934X_RCO_CAL_OUT_1,                           0x00 },
	{ WCD934X_RCO_CAL_OUT_2,                           0x00 },
	{ WCD934X_RCO_CAL_OUT_3,                           0x00 },
	{ WCD934X_RCO_CAL_OUT_4,                           0x00 },
	{ WCD934X_RCO_CAL_OUT_5,                           0x00 },
	{ WCD934X_SIDO_MODE_1,                             0x84 },
	{ WCD934X_SIDO_MODE_2,                             0xfe },
	{ WCD934X_SIDO_MODE_3,                             0xf6 },
	{ WCD934X_SIDO_MODE_4,                             0x56 },
	{ WCD934X_SIDO_VCL_1,                              0x00 },
	{ WCD934X_SIDO_VCL_2,                              0x6c },
	{ WCD934X_SIDO_VCL_3,                              0x44 },
	{ WCD934X_SIDO_CCL_1,                              0x57 },
	{ WCD934X_SIDO_CCL_2,                              0x92 },
	{ WCD934X_SIDO_CCL_3,                              0x35 },
	{ WCD934X_SIDO_CCL_4,                              0x61 },
	{ WCD934X_SIDO_CCL_5,                              0x6d },
	{ WCD934X_SIDO_CCL_6,                              0x60 },
	{ WCD934X_SIDO_CCL_7,                              0x6f },
	{ WCD934X_SIDO_CCL_8,                              0x6f },
	{ WCD934X_SIDO_CCL_9,                              0x6e },
	{ WCD934X_SIDO_CCL_10,                             0x26 },
	{ WCD934X_SIDO_FILTER_1,                           0x92 },
	{ WCD934X_SIDO_FILTER_2,                           0x54 },
	{ WCD934X_SIDO_DRIVER_1,                           0x77 },
	{ WCD934X_SIDO_DRIVER_2,                           0x55 },
	{ WCD934X_SIDO_DRIVER_3,                           0x55 },
	{ WCD934X_SIDO_CAL_CODE_EXT_1,                     0x9c },
	{ WCD934X_SIDO_CAL_CODE_EXT_2,                     0x82 },
	{ WCD934X_SIDO_CAL_CODE_OUT_1,                     0x00 },
	{ WCD934X_SIDO_CAL_CODE_OUT_2,                     0x00 },
	{ WCD934X_SIDO_TEST_1,                             0x00 },
	{ WCD934X_SIDO_TEST_2,                             0x00 },
	{ WCD934X_MBHC_CTL_CLK,                            0x30 },
	{ WCD934X_MBHC_CTL_ANA,                            0x00 },
	{ WCD934X_MBHC_CTL_SPARE_1,                        0x00 },
	{ WCD934X_MBHC_CTL_SPARE_2,                        0x00 },
	{ WCD934X_MBHC_CTL_BCS,                            0x00 },
	{ WCD934X_MBHC_STATUS_SPARE_1,                     0x00 },
	{ WCD934X_MBHC_TEST_CTL,                           0x00 },
	{ WCD934X_VBADC_SUBBLOCK_EN,                       0xde },
	{ WCD934X_VBADC_IBIAS_FE,                          0x58 },
	{ WCD934X_VBADC_BIAS_ADC,                          0x51 },
	{ WCD934X_VBADC_FE_CTRL,                           0x1c },
	{ WCD934X_VBADC_ADC_REF,                           0x20 },
	{ WCD934X_VBADC_ADC_IO,                            0x80 },
	{ WCD934X_VBADC_ADC_SAR,                           0xff },
	{ WCD934X_VBADC_DEBUG,                             0x00 },
	{ WCD934X_LDOH_MODE,                               0x2b },
	{ WCD934X_LDOH_BIAS,                               0x68 },
	{ WCD934X_LDOH_STB_LOADS,                          0x00 },
	{ WCD934X_LDOH_SLOWRAMP,                           0x50 },
	{ WCD934X_MICB1_TEST_CTL_1,                        0x1a },
	{ WCD934X_MICB1_TEST_CTL_2,                        0x18 },
	{ WCD934X_MICB1_TEST_CTL_3,                        0xa4 },
	{ WCD934X_MICB2_TEST_CTL_1,                        0x1a },
	{ WCD934X_MICB2_TEST_CTL_2,                        0x18 },
	{ WCD934X_MICB2_TEST_CTL_3,                        0xa4 },
	{ WCD934X_MICB3_TEST_CTL_1,                        0x1a },
	{ WCD934X_MICB3_TEST_CTL_2,                        0x18 },
	{ WCD934X_MICB3_TEST_CTL_3,                        0xa4 },
	{ WCD934X_MICB4_TEST_CTL_1,                        0x1a },
	{ WCD934X_MICB4_TEST_CTL_2,                        0x18 },
	{ WCD934X_MICB4_TEST_CTL_3,                        0xa4 },
	{ WCD934X_TX_COM_ADC_VCM,                          0x39 },
	{ WCD934X_TX_COM_BIAS_ATEST,                       0xc0 },
	{ WCD934X_TX_COM_ADC_INT1_IB,                      0x6f },
	{ WCD934X_TX_COM_ADC_INT2_IB,                      0x4f },
	{ WCD934X_TX_COM_TXFE_DIV_CTL,                     0x2e },
	{ WCD934X_TX_COM_TXFE_DIV_START,                   0x00 },
	{ WCD934X_TX_COM_TXFE_DIV_STOP_9P6M,               0xc7 },
	{ WCD934X_TX_COM_TXFE_DIV_STOP_12P288M,            0xff },
	{ WCD934X_TX_1_2_TEST_EN,                          0xcc },
	{ WCD934X_TX_1_2_ADC_IB,                           0x09 },
	{ WCD934X_TX_1_2_ATEST_REFCTL,                     0x0a },
	{ WCD934X_TX_1_2_TEST_CTL,                         0x38 },
	{ WCD934X_TX_1_2_TEST_BLK_EN,                      0xff },
	{ WCD934X_TX_1_2_TXFE_CLKDIV,                      0x00 },
	{ WCD934X_TX_1_2_SAR1_ERR,                         0x00 },
	{ WCD934X_TX_1_2_SAR2_ERR,                         0x00 },
	{ WCD934X_TX_3_4_TEST_EN,                          0xcc },
	{ WCD934X_TX_3_4_ADC_IB,                           0x09 },
	{ WCD934X_TX_3_4_ATEST_REFCTL,                     0x0a },
	{ WCD934X_TX_3_4_TEST_CTL,                         0x38 },
	{ WCD934X_TX_3_4_TEST_BLK_EN,                      0xff },
	{ WCD934X_TX_3_4_TXFE_CLKDIV,                      0x00 },
	{ WCD934X_TX_3_4_SAR1_ERR,                         0x00 },
	{ WCD934X_TX_3_4_SAR2_ERR,                         0x00 },
	{ WCD934X_CLASSH_MODE_1,                           0x40 },
	{ WCD934X_CLASSH_MODE_2,                           0x3a },
	{ WCD934X_CLASSH_MODE_3,                           0x00 },
	{ WCD934X_CLASSH_CTRL_VCL_1,                       0x70 },
	{ WCD934X_CLASSH_CTRL_VCL_2,                       0x82 },
	{ WCD934X_CLASSH_CTRL_CCL_1,                       0x31 },
	{ WCD934X_CLASSH_CTRL_CCL_2,                       0x80 },
	{ WCD934X_CLASSH_CTRL_CCL_3,                       0x80 },
	{ WCD934X_CLASSH_CTRL_CCL_4,                       0x51 },
	{ WCD934X_CLASSH_CTRL_CCL_5,                       0x00 },
	{ WCD934X_CLASSH_BUCK_TMUX_A_D,                    0x00 },
	{ WCD934X_CLASSH_BUCK_SW_DRV_CNTL,                 0x77 },
	{ WCD934X_CLASSH_SPARE,                            0x00 },
	{ WCD934X_FLYBACK_EN,                              0x4e },
	{ WCD934X_FLYBACK_VNEG_CTRL_1,                     0x0b },
	{ WCD934X_FLYBACK_VNEG_CTRL_2,                     0x45 },
	{ WCD934X_FLYBACK_VNEG_CTRL_3,                     0x74 },
	{ WCD934X_FLYBACK_VNEG_CTRL_4,                     0x7f },
	{ WCD934X_FLYBACK_VNEG_CTRL_5,                     0x83 },
	{ WCD934X_FLYBACK_VNEG_CTRL_6,                     0x98 },
	{ WCD934X_FLYBACK_VNEG_CTRL_7,                     0xa9 },
	{ WCD934X_FLYBACK_VNEG_CTRL_8,                     0x68 },
	{ WCD934X_FLYBACK_VNEG_CTRL_9,                     0x64 },
	{ WCD934X_FLYBACK_VNEGDAC_CTRL_1,                  0xed },
	{ WCD934X_FLYBACK_VNEGDAC_CTRL_2,                  0xf0 },
	{ WCD934X_FLYBACK_VNEGDAC_CTRL_3,                  0xa6 },
	{ WCD934X_FLYBACK_CTRL_1,                          0x65 },
	{ WCD934X_FLYBACK_TEST_CTL,                        0x00 },
	{ WCD934X_RX_AUX_SW_CTL,                           0x00 },
	{ WCD934X_RX_PA_AUX_IN_CONN,                       0x00 },
	{ WCD934X_RX_TIMER_DIV,                            0x32 },
	{ WCD934X_RX_OCP_CTL,                              0x1f },
	{ WCD934X_RX_OCP_COUNT,                            0x77 },
	{ WCD934X_RX_BIAS_EAR_DAC,                         0xa0 },
	{ WCD934X_RX_BIAS_EAR_AMP,                         0xaa },
	{ WCD934X_RX_BIAS_HPH_LDO,                         0xa9 },
	{ WCD934X_RX_BIAS_HPH_PA,                          0xaa },
	{ WCD934X_RX_BIAS_HPH_RDACBUFF_CNP2,               0x8a },
	{ WCD934X_RX_BIAS_HPH_RDAC_LDO,                    0x88 },
	{ WCD934X_RX_BIAS_HPH_CNP1,                        0x82 },
	{ WCD934X_RX_BIAS_HPH_LOWPOWER,                    0x82 },
	{ WCD934X_RX_BIAS_DIFFLO_PA,                       0x80 },
	{ WCD934X_RX_BIAS_DIFFLO_REF,                      0x88 },
	{ WCD934X_RX_BIAS_DIFFLO_LDO,                      0x88 },
	{ WCD934X_RX_BIAS_SELO_DAC_PA,                     0xa8 },
	{ WCD934X_RX_BIAS_BUCK_RST,                        0x08 },
	{ WCD934X_RX_BIAS_BUCK_VREF_ERRAMP,                0x44 },
	{ WCD934X_RX_BIAS_FLYB_ERRAMP,                     0x40 },
	{ WCD934X_RX_BIAS_FLYB_BUFF,                       0xaa },
	{ WCD934X_RX_BIAS_FLYB_MID_RST,                    0x14 },
	{ WCD934X_HPH_L_STATUS,                            0x04 },
	{ WCD934X_HPH_R_STATUS,                            0x04 },
	{ WCD934X_HPH_CNP_EN,                              0x80 },
	{ WCD934X_HPH_CNP_WG_CTL,                          0x9a },
	{ WCD934X_HPH_CNP_WG_TIME,                         0x14 },
	{ WCD934X_HPH_OCP_CTL,                             0x28 },
	{ WCD934X_HPH_AUTO_CHOP,                           0x16 },
	{ WCD934X_HPH_CHOP_CTL,                            0x83 },
	{ WCD934X_HPH_PA_CTL1,                             0x46 },
	{ WCD934X_HPH_PA_CTL2,                             0x50 },
	{ WCD934X_HPH_L_EN,                                0x80 },
	{ WCD934X_HPH_L_TEST,                              0xe0 },
	{ WCD934X_HPH_L_ATEST,                             0x50 },
	{ WCD934X_HPH_R_EN,                                0x80 },
	{ WCD934X_HPH_R_TEST,                              0xe0 },
	{ WCD934X_HPH_R_ATEST,                             0x54 },
	{ WCD934X_HPH_RDAC_CLK_CTL1,                       0x99 },
	{ WCD934X_HPH_RDAC_CLK_CTL2,                       0x9b },
	{ WCD934X_HPH_RDAC_LDO_CTL,                        0x33 },
	{ WCD934X_HPH_RDAC_CHOP_CLK_LP_CTL,                0x00 },
	{ WCD934X_HPH_REFBUFF_UHQA_CTL,                    0xa8 },
	{ WCD934X_HPH_REFBUFF_LP_CTL,                      0x0a },
	{ WCD934X_HPH_L_DAC_CTL,                           0x00 },
	{ WCD934X_HPH_R_DAC_CTL,                           0x00 },
	{ WCD934X_EAR_EN_REG,                              0x60 },
	{ WCD934X_EAR_CMBUFF,                              0x05 },
	{ WCD934X_EAR_ICTL,                                0x40 },
	{ WCD934X_EAR_EN_DBG_CTL,                          0x00 },
	{ WCD934X_EAR_CNP,                                 0xe0 },
	{ WCD934X_EAR_DAC_CTL_ATEST,                       0x00 },
	{ WCD934X_EAR_STATUS_REG,                          0x04 },
	{ WCD934X_EAR_EAR_MISC,                            0x28 },
	{ WCD934X_DIFF_LO_MISC,                            0x03 },
	{ WCD934X_DIFF_LO_LO2_COMPANDER,                   0x00 },
	{ WCD934X_DIFF_LO_LO1_COMPANDER,                   0x00 },
	{ WCD934X_DIFF_LO_COMMON,                          0x40 },
	{ WCD934X_DIFF_LO_BYPASS_EN,                       0x00 },
	{ WCD934X_DIFF_LO_CNP,                             0x20 },
	{ WCD934X_DIFF_LO_CORE_OUT_PROG,                   0xa0 },
	{ WCD934X_DIFF_LO_LDO_OUT_PROG,                    0x00 },
	{ WCD934X_DIFF_LO_COM_SWCAP_REFBUF_FREQ,           0x8b },
	{ WCD934X_DIFF_LO_COM_PA_FREQ,                     0xb0 },
	{ WCD934X_DIFF_LO_RESERVED_REG,                    0x60 },
	{ WCD934X_DIFF_LO_LO1_STATUS_1,                    0x00 },
	{ WCD934X_DIFF_LO_LO1_STATUS_2,                    0x00 },
	{ WCD934X_ANA_NEW_PAGE_REGISTER,                   0x00 },
	{ WCD934X_HPH_NEW_ANA_HPH2,                        0x00 },
	{ WCD934X_HPH_NEW_ANA_HPH3,                        0x00 },
	{ WCD934X_SLNQ_ANA_EN,                             0x02 },
	{ WCD934X_SLNQ_ANA_STATUS,                         0x00 },
	{ WCD934X_SLNQ_ANA_LDO_CONFIG,                     0xea },
	{ WCD934X_SLNQ_ANA_LDO_OCP_CONFIG,                 0x95 },
	{ WCD934X_SLNQ_ANA_TX_LDO_CONFIG,                  0xb6 },
	{ WCD934X_SLNQ_ANA_TX_DRV_CONFIG,                  0x26 },
	{ WCD934X_SLNQ_ANA_RX_CONFIG_1,                    0x64 },
	{ WCD934X_SLNQ_ANA_RX_CONFIG_2,                    0x40 },
	{ WCD934X_SLNQ_ANA_PLL_ENABLES,                    0x00 },
	{ WCD934X_SLNQ_ANA_PLL_PRESET,                     0x08 },
	{ WCD934X_SLNQ_ANA_PLL_STATUS,                     0x00 },
	{ WCD934X_CLK_SYS_PLL_ENABLES,                     0x00 },
	{ WCD934X_CLK_SYS_PLL_PRESET,                      0x00 },
	{ WCD934X_CLK_SYS_PLL_STATUS,                      0x00 },
	{ WCD934X_CLK_SYS_MCLK_PRG,                        0x00 },
	{ WCD934X_CLK_SYS_MCLK2_PRG1,                      0x00 },
	{ WCD934X_CLK_SYS_MCLK2_PRG2,                      0x00 },
	{ WCD934X_CLK_SYS_XO_PRG,                          0x00 },
	{ WCD934X_CLK_SYS_XO_CAP_XTP,                      0x00 },
	{ WCD934X_CLK_SYS_XO_CAP_XTM,                      0x00 },
	{ WCD934X_BOOST_BST_EN_DLY,                        0x40 },
	{ WCD934X_BOOST_CTRL_ILIM,                         0x9c },
	{ WCD934X_BOOST_VOUT_SETTING,                      0xca },
	{ WCD934X_SIDO_NEW_VOUT_A_STARTUP,                 0x05 },
	{ WCD934X_SIDO_NEW_VOUT_D_STARTUP,                 0x0d },
	{ WCD934X_SIDO_NEW_VOUT_D_FREQ1,                   0x07 },
	{ WCD934X_SIDO_NEW_VOUT_D_FREQ2,                   0x00 },
	{ WCD934X_MBHC_NEW_ELECT_REM_CLAMP_CTL,            0x00 },
	{ WCD934X_MBHC_NEW_CTL_1,                          0x02 },
	{ WCD934X_MBHC_NEW_CTL_2,                          0x05 },
	{ WCD934X_MBHC_NEW_PLUG_DETECT_CTL,                0xe9 },
	{ WCD934X_MBHC_NEW_ZDET_ANA_CTL,                   0x0f },
	{ WCD934X_MBHC_NEW_ZDET_RAMP_CTL,                  0x00 },
	{ WCD934X_MBHC_NEW_FSM_STATUS,                     0x00 },
	{ WCD934X_MBHC_NEW_ADC_RESULT,                     0x00 },
	{ WCD934X_TX_NEW_AMIC_4_5_SEL,                     0x00 },
	{ WCD934X_VBADC_NEW_ADC_MODE,                      0x10 },
	{ WCD934X_VBADC_NEW_ADC_DOUTMSB,                   0x00 },
	{ WCD934X_VBADC_NEW_ADC_DOUTLSB,                   0x00 },
	{ WCD934X_HPH_NEW_INT_RDAC_GAIN_CTL,               0x00 },
	{ WCD934X_HPH_NEW_INT_RDAC_HD2_CTL,                0xa0 },
	{ WCD934X_HPH_NEW_INT_RDAC_VREF_CTL,               0x10 },
	{ WCD934X_HPH_NEW_INT_RDAC_OVERRIDE_CTL,           0x00 },
	{ WCD934X_HPH_NEW_INT_RDAC_MISC1,                  0x00 },
	{ WCD934X_HPH_NEW_INT_PA_MISC1,                    0x22 },
	{ WCD934X_HPH_NEW_INT_PA_MISC2,                    0x00 },
	{ WCD934X_HPH_NEW_INT_PA_RDAC_MISC,                0x00 },
	{ WCD934X_HPH_NEW_INT_HPH_TIMER1,                  0xfe },
	{ WCD934X_HPH_NEW_INT_HPH_TIMER2,                  0x02 },
	{ WCD934X_HPH_NEW_INT_HPH_TIMER3,                  0x4e },
	{ WCD934X_HPH_NEW_INT_HPH_TIMER4,                  0x54 },
	{ WCD934X_HPH_NEW_INT_PA_RDAC_MISC2,               0x00 },
	{ WCD934X_HPH_NEW_INT_PA_RDAC_MISC3,               0x00 },
	{ WCD934X_RX_NEW_INT_HPH_RDAC_BIAS_LOHIFI,         0x62 },
	{ WCD934X_RX_NEW_INT_HPH_RDAC_BIAS_ULP,            0x01 },
	{ WCD934X_RX_NEW_INT_HPH_RDAC_LDO_LP,              0x11 },
	{ WCD934X_SLNQ_INT_ANA_INT_LDO_TEST,               0x0d },
	{ WCD934X_SLNQ_INT_ANA_INT_LDO_DEBUG_1,            0x85 },
	{ WCD934X_SLNQ_INT_ANA_INT_LDO_DEBUG_2,            0xb4 },
	{ WCD934X_SLNQ_INT_ANA_INT_TX_LDO_TEST,            0x16 },
	{ WCD934X_SLNQ_INT_ANA_INT_TX_DRV_TEST,            0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_RX_TEST,                0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_RX_TEST_STATUS,         0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_RX_DEBUG_1,             0x50 },
	{ WCD934X_SLNQ_INT_ANA_INT_RX_DEBUG_2,             0x04 },
	{ WCD934X_SLNQ_INT_ANA_INT_CLK_CTRL,               0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_RESERVED_1,             0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_RESERVED_2,             0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_POST_DIV_REG0,      0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_POST_DIV_REG1,      0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_REF_DIV_REG0,       0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_REF_DIV_REG1,       0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_FILTER_REG0,        0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_FILTER_REG1,        0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_L_VAL,              0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_M_VAL,              0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_N_VAL,              0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_TEST_REG0,          0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_PFD_CP_DSM_PROG,    0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_VCO_PROG,           0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_TEST_REG1,          0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_LDO_LOCK_CFG,       0x00 },
	{ WCD934X_SLNQ_INT_ANA_INT_PLL_DIG_LOCK_DET_CFG,   0x00 },
	{ WCD934X_CLK_SYS_INT_POST_DIV_REG0,               0x00 },
	{ WCD934X_CLK_SYS_INT_POST_DIV_REG1,               0x00 },
	{ WCD934X_CLK_SYS_INT_REF_DIV_REG0,                0x00 },
	{ WCD934X_CLK_SYS_INT_REF_DIV_REG1,                0x00 },
	{ WCD934X_CLK_SYS_INT_FILTER_REG0,                 0x00 },
	{ WCD934X_CLK_SYS_INT_FILTER_REG1,                 0x00 },
	{ WCD934X_CLK_SYS_INT_PLL_L_VAL,                   0x00 },
	{ WCD934X_CLK_SYS_INT_PLL_M_VAL,                   0x00 },
	{ WCD934X_CLK_SYS_INT_PLL_N_VAL,                   0x00 },
	{ WCD934X_CLK_SYS_INT_TEST_REG0,                   0x00 },
	{ WCD934X_CLK_SYS_INT_PFD_CP_DSM_PROG,             0x00 },
	{ WCD934X_CLK_SYS_INT_VCO_PROG,                    0x00 },
	{ WCD934X_CLK_SYS_INT_TEST_REG1,                   0x00 },
	{ WCD934X_CLK_SYS_INT_LDO_LOCK_CFG,                0x00 },
	{ WCD934X_CLK_SYS_INT_DIG_LOCK_DET_CFG,            0x00 },
	{ WCD934X_CLK_SYS_INT_CLK_TEST1,                   0x00 },
	{ WCD934X_CLK_SYS_INT_CLK_TEST2,                   0x00 },
	{ WCD934X_CLK_SYS_INT_CLK_TEST3,                   0x00 },
	{ WCD934X_CLK_SYS_INT_XO_TEST1,                    0x98 },
	{ WCD934X_CLK_SYS_INT_XO_TEST2,                    0x00 },
	{ WCD934X_BOOST_INT_VCOMP_HYST,                    0x02 },
	{ WCD934X_BOOST_INT_VLOOP_FILTER,                  0xef },
	{ WCD934X_BOOST_INT_CTRL_IDELTA,                   0xa8 },
	{ WCD934X_BOOST_INT_CTRL_ILIM_STARTUP,             0x17 },
	{ WCD934X_BOOST_INT_CTRL_MIN_ONTIME,               0x5f },
	{ WCD934X_BOOST_INT_CTRL_MAX_ONTIME,               0x88 },
	{ WCD934X_BOOST_INT_CTRL_TIMING,                   0x0a },
	{ WCD934X_BOOST_INT_TMUX_A_D,                      0x00 },
	{ WCD934X_BOOST_INT_SW_DRV_CNTL,                   0xf8 },
	{ WCD934X_BOOST_INT_SPARE1,                        0x00 },
	{ WCD934X_BOOST_INT_SPARE2,                        0x00 },
	{ WCD934X_SIDO_NEW_INT_RAMP_STATUS,                0x00 },
	{ WCD934X_SIDO_NEW_INT_SPARE_1,                    0x00 },
	{ WCD934X_SIDO_NEW_INT_DEBUG_VOUT_SETTING_A,       0x64 },
	{ WCD934X_SIDO_NEW_INT_DEBUG_VOUT_SETTING_D,       0x40 },
	{ WCD934X_SIDO_NEW_INT_RAMP_INC_WAIT,              0x24 },
	{ WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_CTL,          0x09 },
	{ WCD934X_SIDO_NEW_INT_RAMP_IBLEED_CTL,            0x7d },
	{ WCD934X_SIDO_NEW_INT_DEBUG_CPROVR_TEST,          0x00 },
	{ WCD934X_SIDO_NEW_INT_RAMP_CTL_A,                 0x14 },
	{ WCD934X_SIDO_NEW_INT_RAMP_CTL_D,                 0x14 },
	{ WCD934X_SIDO_NEW_INT_RAMP_TIMEOUT_PERIOD,        0x33 },
	{ WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING1,     0x3f },
	{ WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING2,     0x74 },
	{ WCD934X_SIDO_NEW_INT_DYNAMIC_IPEAK_SETTING3,     0x33 },
	{ WCD934X_SIDO_NEW_INT_HIGH_ACCU_MODE_SEL1,        0x1d },
	{ WCD934X_SIDO_NEW_INT_HIGH_ACCU_MODE_SEL2,        0x0a },
	{ WCD934X_MBHC_NEW_INT_SLNQ_HPF,                   0x50 },
	{ WCD934X_MBHC_NEW_INT_SLNQ_REF,                   0x24 },
	{ WCD934X_MBHC_NEW_INT_SLNQ_COMP,                  0x50 },
	{ WCD934X_MBHC_NEW_INT_SPARE_2,                    0x00 },
	{ WCD934X_PAGE10_PAGE_REGISTER,                    0x00 },
	{ WCD934X_CDC_ANC0_CLK_RESET_CTL,                  0x00 },
	{ WCD934X_CDC_ANC0_MODE_1_CTL,                     0x00 },
	{ WCD934X_CDC_ANC0_MODE_2_CTL,                     0x00 },
	{ WCD934X_CDC_ANC0_FF_SHIFT,                       0x00 },
	{ WCD934X_CDC_ANC0_FB_SHIFT,                       0x00 },
	{ WCD934X_CDC_ANC0_LPF_FF_A_CTL,                   0x00 },
	{ WCD934X_CDC_ANC0_LPF_FF_B_CTL,                   0x00 },
	{ WCD934X_CDC_ANC0_LPF_FB_CTL,                     0x00 },
	{ WCD934X_CDC_ANC0_SMLPF_CTL,                      0x00 },
	{ WCD934X_CDC_ANC0_DCFLT_SHIFT_CTL,                0x00 },
	{ WCD934X_CDC_ANC0_IIR_ADAPT_CTL,                  0x00 },
	{ WCD934X_CDC_ANC0_IIR_COEFF_1_CTL,                0x00 },
	{ WCD934X_CDC_ANC0_IIR_COEFF_2_CTL,                0x00 },
	{ WCD934X_CDC_ANC0_FF_A_GAIN_CTL,                  0x00 },
	{ WCD934X_CDC_ANC0_FF_B_GAIN_CTL,                  0x00 },
	{ WCD934X_CDC_ANC0_FB_GAIN_CTL,                    0x00 },
	{ WCD934X_CDC_ANC0_RC_COMMON_CTL,                  0x00 },
	{ WCD934X_CDC_ANC0_FIFO_COMMON_CTL,                0x88 },
	{ WCD934X_CDC_ANC0_RC0_STATUS_FMIN_CNTR,           0x00 },
	{ WCD934X_CDC_ANC0_RC1_STATUS_FMIN_CNTR,           0x00 },
	{ WCD934X_CDC_ANC0_RC0_STATUS_FMAX_CNTR,           0x00 },
	{ WCD934X_CDC_ANC0_RC1_STATUS_FMAX_CNTR,           0x00 },
	{ WCD934X_CDC_ANC0_STATUS_FIFO,                    0x00 },
	{ WCD934X_CDC_ANC1_CLK_RESET_CTL,                  0x00 },
	{ WCD934X_CDC_ANC1_MODE_1_CTL,                     0x00 },
	{ WCD934X_CDC_ANC1_MODE_2_CTL,                     0x00 },
	{ WCD934X_CDC_ANC1_FF_SHIFT,                       0x00 },
	{ WCD934X_CDC_ANC1_FB_SHIFT,                       0x00 },
	{ WCD934X_CDC_ANC1_LPF_FF_A_CTL,                   0x00 },
	{ WCD934X_CDC_ANC1_LPF_FF_B_CTL,                   0x00 },
	{ WCD934X_CDC_ANC1_LPF_FB_CTL,                     0x00 },
	{ WCD934X_CDC_ANC1_SMLPF_CTL,                      0x00 },
	{ WCD934X_CDC_ANC1_DCFLT_SHIFT_CTL,                0x00 },
	{ WCD934X_CDC_ANC1_IIR_ADAPT_CTL,                  0x00 },
	{ WCD934X_CDC_ANC1_IIR_COEFF_1_CTL,                0x00 },
	{ WCD934X_CDC_ANC1_IIR_COEFF_2_CTL,                0x00 },
	{ WCD934X_CDC_ANC1_FF_A_GAIN_CTL,                  0x00 },
	{ WCD934X_CDC_ANC1_FF_B_GAIN_CTL,                  0x00 },
	{ WCD934X_CDC_ANC1_FB_GAIN_CTL,                    0x00 },
	{ WCD934X_CDC_ANC1_RC_COMMON_CTL,                  0x00 },
	{ WCD934X_CDC_ANC1_FIFO_COMMON_CTL,                0x88 },
	{ WCD934X_CDC_ANC1_RC0_STATUS_FMIN_CNTR,           0x00 },
	{ WCD934X_CDC_ANC1_RC1_STATUS_FMIN_CNTR,           0x00 },
	{ WCD934X_CDC_ANC1_RC0_STATUS_FMAX_CNTR,           0x00 },
	{ WCD934X_CDC_ANC1_RC1_STATUS_FMAX_CNTR,           0x00 },
	{ WCD934X_CDC_ANC1_STATUS_FIFO,                    0x00 },
	{ WCD934X_CDC_TX0_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX0_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX0_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX0_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX0_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX0_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX0_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX0_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX0_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX0_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX0_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX0_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX0_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX0_TX_PATH_SEC7,                    0x25 },
	{ WCD934X_CDC_TX1_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX1_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX1_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX1_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX1_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX1_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX1_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX1_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX1_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX1_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX1_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX1_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX1_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX2_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX2_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX2_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX2_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX2_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX2_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX2_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX2_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX2_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX2_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX2_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX2_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX2_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX3_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX3_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX3_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX3_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX3_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX3_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX3_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX3_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX3_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX3_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX3_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX3_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX3_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX4_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX4_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX4_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX4_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX4_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX4_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX4_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX4_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX4_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX4_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX4_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX4_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX4_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX5_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX5_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX5_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX5_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX5_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX5_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX5_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX5_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX5_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX5_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX5_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX5_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX5_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX6_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX6_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX6_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX6_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX6_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX6_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX6_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX6_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX6_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX6_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX6_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX6_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX6_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX7_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX7_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX7_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX7_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX7_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX7_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX7_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX7_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX7_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX7_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX7_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX7_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX7_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX8_TX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_TX8_TX_PATH_CFG0,                    0x10 },
	{ WCD934X_CDC_TX8_TX_PATH_CFG1,                    0x03 },
	{ WCD934X_CDC_TX8_TX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_TX8_TX_PATH_192_CTL,                 0x00 },
	{ WCD934X_CDC_TX8_TX_PATH_192_CFG,                 0x00 },
	{ WCD934X_CDC_TX8_TX_PATH_SEC0,                    0x00 },
	{ WCD934X_CDC_TX8_TX_PATH_SEC1,                    0x00 },
	{ WCD934X_CDC_TX8_TX_PATH_SEC2,                    0x01 },
	{ WCD934X_CDC_TX8_TX_PATH_SEC3,                    0x3c },
	{ WCD934X_CDC_TX8_TX_PATH_SEC4,                    0x20 },
	{ WCD934X_CDC_TX8_TX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_TX8_TX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_TX9_SPKR_PROT_PATH_CTL,              0x02 },
	{ WCD934X_CDC_TX9_SPKR_PROT_PATH_CFG0,             0x00 },
	{ WCD934X_CDC_TX10_SPKR_PROT_PATH_CTL,             0x02 },
	{ WCD934X_CDC_TX10_SPKR_PROT_PATH_CFG0,            0x00 },
	{ WCD934X_CDC_TX11_SPKR_PROT_PATH_CTL,             0x02 },
	{ WCD934X_CDC_TX11_SPKR_PROT_PATH_CFG0,            0x00 },
	{ WCD934X_CDC_TX12_SPKR_PROT_PATH_CTL,             0x02 },
	{ WCD934X_CDC_TX12_SPKR_PROT_PATH_CFG0,            0x00 },
	{ WCD934X_PAGE11_PAGE_REGISTER,                    0x00 },
	{ WCD934X_CDC_COMPANDER1_CTL0,                     0x60 },
	{ WCD934X_CDC_COMPANDER1_CTL1,                     0xdb },
	{ WCD934X_CDC_COMPANDER1_CTL2,                     0xff },
	{ WCD934X_CDC_COMPANDER1_CTL3,                     0x35 },
	{ WCD934X_CDC_COMPANDER1_CTL4,                     0xff },
	{ WCD934X_CDC_COMPANDER1_CTL5,                     0x00 },
	{ WCD934X_CDC_COMPANDER1_CTL6,                     0x01 },
	{ WCD934X_CDC_COMPANDER1_CTL7,                     0x08 },
	{ WCD934X_CDC_COMPANDER2_CTL0,                     0x60 },
	{ WCD934X_CDC_COMPANDER2_CTL1,                     0xdb },
	{ WCD934X_CDC_COMPANDER2_CTL2,                     0xff },
	{ WCD934X_CDC_COMPANDER2_CTL3,                     0x35 },
	{ WCD934X_CDC_COMPANDER2_CTL4,                     0xff },
	{ WCD934X_CDC_COMPANDER2_CTL5,                     0x00 },
	{ WCD934X_CDC_COMPANDER2_CTL6,                     0x01 },
	{ WCD934X_CDC_COMPANDER2_CTL7,                     0x08 },
	{ WCD934X_CDC_COMPANDER3_CTL0,                     0x60 },
	{ WCD934X_CDC_COMPANDER3_CTL1,                     0xdb },
	{ WCD934X_CDC_COMPANDER3_CTL2,                     0xff },
	{ WCD934X_CDC_COMPANDER3_CTL3,                     0x35 },
	{ WCD934X_CDC_COMPANDER3_CTL4,                     0xff },
	{ WCD934X_CDC_COMPANDER3_CTL5,                     0x00 },
	{ WCD934X_CDC_COMPANDER3_CTL6,                     0x01 },
	{ WCD934X_CDC_COMPANDER3_CTL7,                     0x08 },
	{ WCD934X_CDC_COMPANDER4_CTL0,                     0x60 },
	{ WCD934X_CDC_COMPANDER4_CTL1,                     0xdb },
	{ WCD934X_CDC_COMPANDER4_CTL2,                     0xff },
	{ WCD934X_CDC_COMPANDER4_CTL3,                     0x35 },
	{ WCD934X_CDC_COMPANDER4_CTL4,                     0xff },
	{ WCD934X_CDC_COMPANDER4_CTL5,                     0x00 },
	{ WCD934X_CDC_COMPANDER4_CTL6,                     0x01 },
	{ WCD934X_CDC_COMPANDER4_CTL7,                     0x08 },
	{ WCD934X_CDC_COMPANDER7_CTL0,                     0x60 },
	{ WCD934X_CDC_COMPANDER7_CTL1,                     0xdb },
	{ WCD934X_CDC_COMPANDER7_CTL2,                     0xff },
	{ WCD934X_CDC_COMPANDER7_CTL3,                     0x35 },
	{ WCD934X_CDC_COMPANDER7_CTL4,                     0xff },
	{ WCD934X_CDC_COMPANDER7_CTL5,                     0x00 },
	{ WCD934X_CDC_COMPANDER7_CTL6,                     0x01 },
	{ WCD934X_CDC_COMPANDER7_CTL7,                     0x08 },
	{ WCD934X_CDC_COMPANDER8_CTL0,                     0x60 },
	{ WCD934X_CDC_COMPANDER8_CTL1,                     0xdb },
	{ WCD934X_CDC_COMPANDER8_CTL2,                     0xff },
	{ WCD934X_CDC_COMPANDER8_CTL3,                     0x35 },
	{ WCD934X_CDC_COMPANDER8_CTL4,                     0xff },
	{ WCD934X_CDC_COMPANDER8_CTL5,                     0x00 },
	{ WCD934X_CDC_COMPANDER8_CTL6,                     0x01 },
	{ WCD934X_CDC_COMPANDER8_CTL7,                     0x08 },
	{ WCD934X_CDC_RX0_RX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_RX0_RX_PATH_CFG0,                    0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_CFG1,                    0x64 },
	{ WCD934X_CDC_RX0_RX_PATH_CFG2,                    0x8f },
	{ WCD934X_CDC_RX0_RX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_MIX_CTL,                 0x04 },
	{ WCD934X_CDC_RX0_RX_PATH_MIX_CFG,                 0x7e },
	{ WCD934X_CDC_RX0_RX_VOL_MIX_CTL,                  0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_SEC0,                    0xfc },
	{ WCD934X_CDC_RX0_RX_PATH_SEC1,                    0x08 },
	{ WCD934X_CDC_RX0_RX_PATH_SEC2,                    0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_SEC3,                    0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_SEC7,                    0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_MIX_SEC0,                0x08 },
	{ WCD934X_CDC_RX0_RX_PATH_MIX_SEC1,                0x00 },
	{ WCD934X_CDC_RX0_RX_PATH_DSMDEM_CTL,              0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_RX1_RX_PATH_CFG0,                    0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_CFG1,                    0x64 },
	{ WCD934X_CDC_RX1_RX_PATH_CFG2,                    0x8f },
	{ WCD934X_CDC_RX1_RX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_MIX_CTL,                 0x04 },
	{ WCD934X_CDC_RX1_RX_PATH_MIX_CFG,                 0x7e },
	{ WCD934X_CDC_RX1_RX_VOL_MIX_CTL,                  0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_SEC0,                    0xfc },
	{ WCD934X_CDC_RX1_RX_PATH_SEC1,                    0x08 },
	{ WCD934X_CDC_RX1_RX_PATH_SEC2,                    0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_SEC3,                    0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_SEC4,                    0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_SEC7,                    0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_MIX_SEC0,                0x08 },
	{ WCD934X_CDC_RX1_RX_PATH_MIX_SEC1,                0x00 },
	{ WCD934X_CDC_RX1_RX_PATH_DSMDEM_CTL,              0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_RX2_RX_PATH_CFG0,                    0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_CFG1,                    0x64 },
	{ WCD934X_CDC_RX2_RX_PATH_CFG2,                    0x8f },
	{ WCD934X_CDC_RX2_RX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_MIX_CTL,                 0x04 },
	{ WCD934X_CDC_RX2_RX_PATH_MIX_CFG,                 0x7e },
	{ WCD934X_CDC_RX2_RX_VOL_MIX_CTL,                  0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_SEC0,                    0xfc },
	{ WCD934X_CDC_RX2_RX_PATH_SEC1,                    0x08 },
	{ WCD934X_CDC_RX2_RX_PATH_SEC2,                    0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_SEC3,                    0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_SEC4,                    0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_SEC7,                    0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_MIX_SEC0,                0x08 },
	{ WCD934X_CDC_RX2_RX_PATH_MIX_SEC1,                0x00 },
	{ WCD934X_CDC_RX2_RX_PATH_DSMDEM_CTL,              0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_RX3_RX_PATH_CFG0,                    0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_CFG1,                    0x64 },
	{ WCD934X_CDC_RX3_RX_PATH_CFG2,                    0x8f },
	{ WCD934X_CDC_RX3_RX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_MIX_CTL,                 0x04 },
	{ WCD934X_CDC_RX3_RX_PATH_MIX_CFG,                 0x7e },
	{ WCD934X_CDC_RX3_RX_VOL_MIX_CTL,                  0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_SEC0,                    0xfc },
	{ WCD934X_CDC_RX3_RX_PATH_SEC1,                    0x08 },
	{ WCD934X_CDC_RX3_RX_PATH_SEC2,                    0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_SEC3,                    0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_SEC7,                    0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_MIX_SEC0,                0x08 },
	{ WCD934X_CDC_RX3_RX_PATH_MIX_SEC1,                0x00 },
	{ WCD934X_CDC_RX3_RX_PATH_DSMDEM_CTL,              0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_RX4_RX_PATH_CFG0,                    0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_CFG1,                    0x64 },
	{ WCD934X_CDC_RX4_RX_PATH_CFG2,                    0x8f },
	{ WCD934X_CDC_RX4_RX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_MIX_CTL,                 0x04 },
	{ WCD934X_CDC_RX4_RX_PATH_MIX_CFG,                 0x7e },
	{ WCD934X_CDC_RX4_RX_VOL_MIX_CTL,                  0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_SEC0,                    0xfc },
	{ WCD934X_CDC_RX4_RX_PATH_SEC1,                    0x08 },
	{ WCD934X_CDC_RX4_RX_PATH_SEC2,                    0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_SEC3,                    0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_SEC7,                    0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_MIX_SEC0,                0x08 },
	{ WCD934X_CDC_RX4_RX_PATH_MIX_SEC1,                0x00 },
	{ WCD934X_CDC_RX4_RX_PATH_DSMDEM_CTL,              0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_RX7_RX_PATH_CFG0,                    0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_CFG1,                    0x64 },
	{ WCD934X_CDC_RX7_RX_PATH_CFG2,                    0x8f },
	{ WCD934X_CDC_RX7_RX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_MIX_CTL,                 0x04 },
	{ WCD934X_CDC_RX7_RX_PATH_MIX_CFG,                 0x7e },
	{ WCD934X_CDC_RX7_RX_VOL_MIX_CTL,                  0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_SEC0,                    0x04 },
	{ WCD934X_CDC_RX7_RX_PATH_SEC1,                    0x08 },
	{ WCD934X_CDC_RX7_RX_PATH_SEC2,                    0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_SEC3,                    0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_SEC7,                    0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_MIX_SEC0,                0x08 },
	{ WCD934X_CDC_RX7_RX_PATH_MIX_SEC1,                0x00 },
	{ WCD934X_CDC_RX7_RX_PATH_DSMDEM_CTL,              0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_CTL,                     0x04 },
	{ WCD934X_CDC_RX8_RX_PATH_CFG0,                    0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_CFG1,                    0x64 },
	{ WCD934X_CDC_RX8_RX_PATH_CFG2,                    0x8f },
	{ WCD934X_CDC_RX8_RX_VOL_CTL,                      0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_MIX_CTL,                 0x04 },
	{ WCD934X_CDC_RX8_RX_PATH_MIX_CFG,                 0x7e },
	{ WCD934X_CDC_RX8_RX_VOL_MIX_CTL,                  0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_SEC0,                    0x04 },
	{ WCD934X_CDC_RX8_RX_PATH_SEC1,                    0x08 },
	{ WCD934X_CDC_RX8_RX_PATH_SEC2,                    0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_SEC3,                    0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_SEC5,                    0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_SEC6,                    0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_SEC7,                    0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_MIX_SEC0,                0x08 },
	{ WCD934X_CDC_RX8_RX_PATH_MIX_SEC1,                0x00 },
	{ WCD934X_CDC_RX8_RX_PATH_DSMDEM_CTL,              0x00 },
	{ WCD934X_PAGE12_PAGE_REGISTER,                    0x00 },
	{ WCD934X_CDC_CLSH_CRC,                            0x00 },
	{ WCD934X_CDC_CLSH_DLY_CTRL,                       0x03 },
	{ WCD934X_CDC_CLSH_DECAY_CTRL,                     0x02 },
	{ WCD934X_CDC_CLSH_HPH_V_PA,                       0x1c },
	{ WCD934X_CDC_CLSH_EAR_V_PA,                       0x39 },
	{ WCD934X_CDC_CLSH_HPH_V_HD,                       0x0c },
	{ WCD934X_CDC_CLSH_EAR_V_HD,                       0x0c },
	{ WCD934X_CDC_CLSH_K1_MSB,                         0x01 },
	{ WCD934X_CDC_CLSH_K1_LSB,                         0x00 },
	{ WCD934X_CDC_CLSH_K2_MSB,                         0x00 },
	{ WCD934X_CDC_CLSH_K2_LSB,                         0x80 },
	{ WCD934X_CDC_CLSH_IDLE_CTRL,                      0x00 },
	{ WCD934X_CDC_CLSH_IDLE_HPH,                       0x00 },
	{ WCD934X_CDC_CLSH_IDLE_EAR,                       0x00 },
	{ WCD934X_CDC_CLSH_TEST0,                          0x07 },
	{ WCD934X_CDC_CLSH_TEST1,                          0x00 },
	{ WCD934X_CDC_CLSH_OVR_VREF,                       0x00 },
	{ WCD934X_CDC_BOOST0_BOOST_PATH_CTL,               0x00 },
	{ WCD934X_CDC_BOOST0_BOOST_CTL,                    0xb2 },
	{ WCD934X_CDC_BOOST0_BOOST_CFG1,                   0x00 },
	{ WCD934X_CDC_BOOST0_BOOST_CFG2,                   0x00 },
	{ WCD934X_CDC_BOOST1_BOOST_PATH_CTL,               0x00 },
	{ WCD934X_CDC_BOOST1_BOOST_CTL,                    0xb2 },
	{ WCD934X_CDC_BOOST1_BOOST_CFG1,                   0x00 },
	{ WCD934X_CDC_BOOST1_BOOST_CFG2,                   0x00 },
	{ WCD934X_CDC_VBAT_VBAT_PATH_CTL,                  0x00 },
	{ WCD934X_CDC_VBAT_VBAT_CFG,                       0x1a },
	{ WCD934X_CDC_VBAT_VBAT_ADC_CAL1,                  0x00 },
	{ WCD934X_CDC_VBAT_VBAT_ADC_CAL2,                  0x00 },
	{ WCD934X_CDC_VBAT_VBAT_ADC_CAL3,                  0x04 },
	{ WCD934X_CDC_VBAT_VBAT_PK_EST1,                   0xe0 },
	{ WCD934X_CDC_VBAT_VBAT_PK_EST2,                   0x01 },
	{ WCD934X_CDC_VBAT_VBAT_PK_EST3,                   0x40 },
	{ WCD934X_CDC_VBAT_VBAT_RF_PROC1,                  0x2a },
	{ WCD934X_CDC_VBAT_VBAT_RF_PROC2,                  0x86 },
	{ WCD934X_CDC_VBAT_VBAT_TAC1,                      0x70 },
	{ WCD934X_CDC_VBAT_VBAT_TAC2,                      0x18 },
	{ WCD934X_CDC_VBAT_VBAT_TAC3,                      0x18 },
	{ WCD934X_CDC_VBAT_VBAT_TAC4,                      0x03 },
	{ WCD934X_CDC_VBAT_VBAT_GAIN_UPD1,                 0x01 },
	{ WCD934X_CDC_VBAT_VBAT_GAIN_UPD2,                 0x00 },
	{ WCD934X_CDC_VBAT_VBAT_GAIN_UPD3,                 0x64 },
	{ WCD934X_CDC_VBAT_VBAT_GAIN_UPD4,                 0x01 },
	{ WCD934X_CDC_VBAT_VBAT_DEBUG1,                    0x00 },
	{ WCD934X_CDC_VBAT_VBAT_GAIN_UPD_MON,              0x00 },
	{ WCD934X_CDC_VBAT_VBAT_GAIN_MON_VAL,              0x00 },
	{ WCD934X_CDC_VBAT_VBAT_BAN,                       0x0c },
	{ WCD934X_MIXING_ASRC0_CLK_RST_CTL,                0x00 },
	{ WCD934X_MIXING_ASRC0_CTL0,                       0x00 },
	{ WCD934X_MIXING_ASRC0_CTL1,                       0x00 },
	{ WCD934X_MIXING_ASRC0_FIFO_CTL,                   0xa8 },
	{ WCD934X_MIXING_ASRC0_STATUS_FMIN_CNTR_LSB,       0x00 },
	{ WCD934X_MIXING_ASRC0_STATUS_FMIN_CNTR_MSB,       0x00 },
	{ WCD934X_MIXING_ASRC0_STATUS_FMAX_CNTR_LSB,       0x00 },
	{ WCD934X_MIXING_ASRC0_STATUS_FMAX_CNTR_MSB,       0x00 },
	{ WCD934X_MIXING_ASRC0_STATUS_FIFO,                0x00 },
	{ WCD934X_MIXING_ASRC1_CLK_RST_CTL,                0x00 },
	{ WCD934X_MIXING_ASRC1_CTL0,                       0x00 },
	{ WCD934X_MIXING_ASRC1_CTL1,                       0x00 },
	{ WCD934X_MIXING_ASRC1_FIFO_CTL,                   0xa8 },
	{ WCD934X_MIXING_ASRC1_STATUS_FMIN_CNTR_LSB,       0x00 },
	{ WCD934X_MIXING_ASRC1_STATUS_FMIN_CNTR_MSB,       0x00 },
	{ WCD934X_MIXING_ASRC1_STATUS_FMAX_CNTR_LSB,       0x00 },
	{ WCD934X_MIXING_ASRC1_STATUS_FMAX_CNTR_MSB,       0x00 },
	{ WCD934X_MIXING_ASRC1_STATUS_FIFO,                0x00 },
	{ WCD934X_MIXING_ASRC2_CLK_RST_CTL,                0x00 },
	{ WCD934X_MIXING_ASRC2_CTL0,                       0x00 },
	{ WCD934X_MIXING_ASRC2_CTL1,                       0x00 },
	{ WCD934X_MIXING_ASRC2_FIFO_CTL,                   0xa8 },
	{ WCD934X_MIXING_ASRC2_STATUS_FMIN_CNTR_LSB,       0x00 },
	{ WCD934X_MIXING_ASRC2_STATUS_FMIN_CNTR_MSB,       0x00 },
	{ WCD934X_MIXING_ASRC2_STATUS_FMAX_CNTR_LSB,       0x00 },
	{ WCD934X_MIXING_ASRC2_STATUS_FMAX_CNTR_MSB,       0x00 },
	{ WCD934X_MIXING_ASRC2_STATUS_FIFO,                0x00 },
	{ WCD934X_MIXING_ASRC3_CLK_RST_CTL,                0x00 },
	{ WCD934X_MIXING_ASRC3_CTL0,                       0x00 },
	{ WCD934X_MIXING_ASRC3_CTL1,                       0x00 },
	{ WCD934X_MIXING_ASRC3_FIFO_CTL,                   0xa8 },
	{ WCD934X_MIXING_ASRC3_STATUS_FMIN_CNTR_LSB,       0x00 },
	{ WCD934X_MIXING_ASRC3_STATUS_FMIN_CNTR_MSB,       0x00 },
	{ WCD934X_MIXING_ASRC3_STATUS_FMAX_CNTR_LSB,       0x00 },
	{ WCD934X_MIXING_ASRC3_STATUS_FMAX_CNTR_MSB,       0x00 },
	{ WCD934X_MIXING_ASRC3_STATUS_FIFO,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_WR_DATA_0,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_WR_DATA_1,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_WR_DATA_2,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_WR_DATA_3,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_WR_ADDR_0,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_WR_ADDR_1,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_WR_ADDR_2,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_WR_ADDR_3,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_RD_ADDR_0,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_RD_ADDR_1,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_RD_ADDR_2,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_RD_ADDR_3,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_RD_DATA_0,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_RD_DATA_1,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_RD_DATA_2,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_RD_DATA_3,                0x00 },
	{ WCD934X_SWR_AHB_BRIDGE_ACCESS_CFG,               0x0f },
	{ WCD934X_SWR_AHB_BRIDGE_ACCESS_STATUS,            0x03 },
	{ WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CTL,       0x04 },
	{ WCD934X_CDC_SIDETONE_SRC0_ST_SRC_PATH_CFG1,      0x00 },
	{ WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CTL,       0x04 },
	{ WCD934X_CDC_SIDETONE_SRC1_ST_SRC_PATH_CFG1,      0x00 },
	{ WCD934X_SIDETONE_ASRC0_CLK_RST_CTL,              0x00 },
	{ WCD934X_SIDETONE_ASRC0_CTL0,                     0x00 },
	{ WCD934X_SIDETONE_ASRC0_CTL1,                     0x00 },
	{ WCD934X_SIDETONE_ASRC0_FIFO_CTL,                 0xa8 },
	{ WCD934X_SIDETONE_ASRC0_STATUS_FMIN_CNTR_LSB,     0x00 },
	{ WCD934X_SIDETONE_ASRC0_STATUS_FMIN_CNTR_MSB,     0x00 },
	{ WCD934X_SIDETONE_ASRC0_STATUS_FMAX_CNTR_LSB,     0x00 },
	{ WCD934X_SIDETONE_ASRC0_STATUS_FMAX_CNTR_MSB,     0x00 },
	{ WCD934X_SIDETONE_ASRC0_STATUS_FIFO,              0x00 },
	{ WCD934X_SIDETONE_ASRC1_CLK_RST_CTL,              0x00 },
	{ WCD934X_SIDETONE_ASRC1_CTL0,                     0x00 },
	{ WCD934X_SIDETONE_ASRC1_CTL1,                     0x00 },
	{ WCD934X_SIDETONE_ASRC1_FIFO_CTL,                 0xa8 },
	{ WCD934X_SIDETONE_ASRC1_STATUS_FMIN_CNTR_LSB,     0x00 },
	{ WCD934X_SIDETONE_ASRC1_STATUS_FMIN_CNTR_MSB,     0x00 },
	{ WCD934X_SIDETONE_ASRC1_STATUS_FMAX_CNTR_LSB,     0x00 },
	{ WCD934X_SIDETONE_ASRC1_STATUS_FMAX_CNTR_MSB,     0x00 },
	{ WCD934X_SIDETONE_ASRC1_STATUS_FIFO,              0x00 },
	{ WCD934X_EC_REF_HQ0_EC_REF_HQ_PATH_CTL,           0x00 },
	{ WCD934X_EC_REF_HQ0_EC_REF_HQ_CFG0,               0x01 },
	{ WCD934X_EC_REF_HQ1_EC_REF_HQ_PATH_CTL,           0x00 },
	{ WCD934X_EC_REF_HQ1_EC_REF_HQ_CFG0,               0x01 },
	{ WCD934X_EC_ASRC0_CLK_RST_CTL,                    0x00 },
	{ WCD934X_EC_ASRC0_CTL0,                           0x00 },
	{ WCD934X_EC_ASRC0_CTL1,                           0x00 },
	{ WCD934X_EC_ASRC0_FIFO_CTL,                       0xa8 },
	{ WCD934X_EC_ASRC0_STATUS_FMIN_CNTR_LSB,           0x00 },
	{ WCD934X_EC_ASRC0_STATUS_FMIN_CNTR_MSB,           0x00 },
	{ WCD934X_EC_ASRC0_STATUS_FMAX_CNTR_LSB,           0x00 },
	{ WCD934X_EC_ASRC0_STATUS_FMAX_CNTR_MSB,           0x00 },
	{ WCD934X_EC_ASRC0_STATUS_FIFO,                    0x00 },
	{ WCD934X_EC_ASRC1_CLK_RST_CTL,                    0x00 },
	{ WCD934X_EC_ASRC1_CTL0,                           0x00 },
	{ WCD934X_EC_ASRC1_CTL1,                           0x00 },
	{ WCD934X_EC_ASRC1_FIFO_CTL,                       0xa8 },
	{ WCD934X_EC_ASRC1_STATUS_FMIN_CNTR_LSB,           0x00 },
	{ WCD934X_EC_ASRC1_STATUS_FMIN_CNTR_MSB,           0x00 },
	{ WCD934X_EC_ASRC1_STATUS_FMAX_CNTR_LSB,           0x00 },
	{ WCD934X_EC_ASRC1_STATUS_FMAX_CNTR_MSB,           0x00 },
	{ WCD934X_EC_ASRC1_STATUS_FIFO,                    0x00 },
	{ WCD934X_PAGE13_PAGE_REGISTER,                    0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG0,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT0_CFG1,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG0,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT1_CFG1,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG0,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT2_CFG1,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG0,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT3_CFG1,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG0,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT4_CFG1,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG0,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT7_CFG1,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG0,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_INT8_CFG1,             0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG0,              0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG1,              0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG2,              0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG3,              0x00 },
	{ WCD934X_CDC_RX_INP_MUX_RX_MIX_CFG4,              0x00 },
	{ WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG0,        0x00 },
	{ WCD934X_CDC_RX_INP_MUX_SIDETONE_SRC_CFG1,        0x00 },
	{ WCD934X_CDC_RX_INP_MUX_ANC_CFG0,                 0x00 },
	{ WCD934X_CDC_RX_INP_MUX_SPLINE_ASRC_CFG0,         0x00 },
	{ WCD934X_CDC_RX_INP_MUX_EC_REF_HQ_CFG0,           0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX0_CFG1,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX1_CFG1,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX2_CFG1,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX3_CFG1,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX4_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX5_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX6_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX7_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX8_CFG0,            0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX10_CFG0,           0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX11_CFG0,           0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX12_CFG0,           0x00 },
	{ WCD934X_CDC_TX_INP_MUX_ADC_MUX13_CFG0,           0x00 },
	{ WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG0,  0x00 },
	{ WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG1,  0x00 },
	{ WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG2,  0x00 },
	{ WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR0_MIX_CFG3,  0x00 },
	{ WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG0,  0x00 },
	{ WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG1,  0x00 },
	{ WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG2,  0x00 },
	{ WCD934X_CDC_SIDETONE_IIR_INP_MUX_IIR1_MIX_CFG3,  0x00 },
	{ WCD934X_CDC_IF_ROUTER_TX_MUX_CFG0,               0x00 },
	{ WCD934X_CDC_IF_ROUTER_TX_MUX_CFG1,               0x00 },
	{ WCD934X_CDC_IF_ROUTER_TX_MUX_CFG2,               0x00 },
	{ WCD934X_CDC_IF_ROUTER_TX_MUX_CFG3,               0x00 },
	{ WCD934X_CDC_CLK_RST_CTRL_MCLK_CONTROL,           0x00 },
	{ WCD934X_CDC_CLK_RST_CTRL_FS_CNT_CONTROL,         0x0c },
	{ WCD934X_CDC_CLK_RST_CTRL_SWR_CONTROL,            0x00 },
	{ WCD934X_CDC_CLK_RST_CTRL_DSD_CONTROL,            0x00 },
	{ WCD934X_CDC_CLK_RST_CTRL_ASRC_SHARE_CONTROL,     0x0f },
	{ WCD934X_CDC_CLK_RST_CTRL_GFM_CONTROL,            0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_CTL,                0x08 },
	{ WCD934X_CDC_PROX_DETECT_PROX_POLL_PERIOD0,       0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_POLL_PERIOD1,       0x4b },
	{ WCD934X_CDC_PROX_DETECT_PROX_SIG_PATTERN_LSB,    0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_SIG_PATTERN_MSB,    0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_STATUS,             0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_TEST_CTRL,          0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB,      0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB,      0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_LSB_RD,   0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_TEST_BUFF_MSB_RD,   0x00 },
	{ WCD934X_CDC_PROX_DETECT_PROX_CTL_REPEAT_PAT,     0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_PATH_CTL,          0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B1_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B2_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B3_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B4_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B5_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B6_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B7_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_B8_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_CTL,               0x40 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_GAIN_TIMER_CTL,    0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B2_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_PATH_CTL,          0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B1_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B2_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B3_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B4_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B5_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B6_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B7_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_B8_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_CTL,               0x40 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_GAIN_TIMER_CTL,    0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B1_CTL,       0x00 },
	{ WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL,       0x00 },
	{ WCD934X_CDC_TOP_TOP_CFG0,                        0x00 },
	{ WCD934X_CDC_TOP_TOP_CFG1,                        0x00 },
	{ WCD934X_CDC_TOP_TOP_CFG7,                        0x00 },
	{ WCD934X_CDC_TOP_HPHL_COMP_WR_LSB,                0x00 },
	{ WCD934X_CDC_TOP_HPHL_COMP_WR_MSB,                0x00 },
	{ WCD934X_CDC_TOP_HPHL_COMP_LUT,                   0x00 },
	{ WCD934X_CDC_TOP_HPHL_COMP_RD_LSB,                0x00 },
	{ WCD934X_CDC_TOP_HPHL_COMP_RD_MSB,                0x00 },
	{ WCD934X_CDC_TOP_HPHR_COMP_WR_LSB,                0x00 },
	{ WCD934X_CDC_TOP_HPHR_COMP_WR_MSB,                0x00 },
	{ WCD934X_CDC_TOP_HPHR_COMP_LUT,                   0x00 },
	{ WCD934X_CDC_TOP_HPHR_COMP_RD_LSB,                0x00 },
	{ WCD934X_CDC_TOP_HPHR_COMP_RD_MSB,                0x00 },
	{ WCD934X_CDC_TOP_DIFFL_COMP_WR_LSB,               0x00 },
	{ WCD934X_CDC_TOP_DIFFL_COMP_WR_MSB,               0x00 },
	{ WCD934X_CDC_TOP_DIFFL_COMP_LUT,                  0x00 },
	{ WCD934X_CDC_TOP_DIFFL_COMP_RD_LSB,               0x00 },
	{ WCD934X_CDC_TOP_DIFFL_COMP_RD_MSB,               0x00 },
	{ WCD934X_CDC_TOP_DIFFR_COMP_WR_LSB,               0x00 },
	{ WCD934X_CDC_TOP_DIFFR_COMP_WR_MSB,               0x00 },
	{ WCD934X_CDC_TOP_DIFFR_COMP_LUT,                  0x00 },
	{ WCD934X_CDC_TOP_DIFFR_COMP_RD_LSB,               0x00 },
	{ WCD934X_CDC_TOP_DIFFR_COMP_RD_MSB,               0x00 },
	{ WCD934X_CDC_DSD0_PATH_CTL,                       0x00 },
	{ WCD934X_CDC_DSD0_CFG0,                           0x00 },
	{ WCD934X_CDC_DSD0_CFG1,                           0x00 },
	{ WCD934X_CDC_DSD0_CFG2,                           0x42 },
	{ WCD934X_CDC_DSD0_CFG3,                           0x00 },
	{ WCD934X_CDC_DSD0_CFG4,                           0x02 },
	{ WCD934X_CDC_DSD0_CFG5,                           0x00 },
	{ WCD934X_CDC_DSD1_PATH_CTL,                       0x00 },
	{ WCD934X_CDC_DSD1_CFG0,                           0x00 },
	{ WCD934X_CDC_DSD1_CFG1,                           0x00 },
	{ WCD934X_CDC_DSD1_CFG2,                           0x42 },
	{ WCD934X_CDC_DSD1_CFG3,                           0x00 },
	{ WCD934X_CDC_DSD1_CFG4,                           0x02 },
	{ WCD934X_CDC_DSD1_CFG5,                           0x00 },
	{ WCD934X_CDC_RX_IDLE_DET_PATH_CTL,                0x00 },
	{ WCD934X_CDC_RX_IDLE_DET_CFG0,                    0x07 },
	{ WCD934X_CDC_RX_IDLE_DET_CFG1,                    0x3c },
	{ WCD934X_CDC_RX_IDLE_DET_CFG2,                    0x00 },
	{ WCD934X_CDC_RX_IDLE_DET_CFG3,                    0x00 },
	{ WCD934X_PAGE14_PAGE_REGISTER,                    0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_CLK_RST_CTL,            0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_CTL,                    0x09 },
	{ WCD934X_CDC_RATE_EST0_RE_PULSE_SUPR_CTL,         0x06 },
	{ WCD934X_CDC_RATE_EST0_RE_TIMER,                  0x01 },
	{ WCD934X_CDC_RATE_EST0_RE_BW_SW,                  0x20 },
	{ WCD934X_CDC_RATE_EST0_RE_THRESH,                 0xa0 },
	{ WCD934X_CDC_RATE_EST0_RE_STATUS,                 0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_CTRL,              0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_TIMER2,            0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW1,        0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW2,        0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW3,        0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW4,        0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_OFFSET_BW5,        0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW1,         0x08 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW2,         0x07 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW3,         0x05 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW4,         0x05 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMIT_BW5,         0x05 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW1,       0x08 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW2,       0x07 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW3,       0x05 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW4,       0x05 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_LIMITD1_BW5,       0x05 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW1,          0x03 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW2,          0x03 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW3,          0x03 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW4,          0x03 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_HYST_BW5,          0x03 },
	{ WCD934X_CDC_RATE_EST0_RE_RMAX_DIAG,              0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_RMIN_DIAG,              0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_PH_DET,                 0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_DIAG_CLR,               0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_MB_SW_STATE,            0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_MAST_DIAG_STATE,        0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_RATE_OUT_7_0,           0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_RATE_OUT_15_8,          0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_RATE_OUT_23_16,         0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_RATE_OUT_31_24,         0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_RATE_OUT_39_32,         0x00 },
	{ WCD934X_CDC_RATE_EST0_RE_RATE_OUT_40_43,         0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_CLK_RST_CTL,            0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_CTL,                    0x09 },
	{ WCD934X_CDC_RATE_EST1_RE_PULSE_SUPR_CTL,         0x06 },
	{ WCD934X_CDC_RATE_EST1_RE_TIMER,                  0x01 },
	{ WCD934X_CDC_RATE_EST1_RE_BW_SW,                  0x20 },
	{ WCD934X_CDC_RATE_EST1_RE_THRESH,                 0xa0 },
	{ WCD934X_CDC_RATE_EST1_RE_STATUS,                 0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_CTRL,              0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_TIMER2,            0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW1,        0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW2,        0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW3,        0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW4,        0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_OFFSET_BW5,        0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW1,         0x08 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW2,         0x07 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW3,         0x05 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW4,         0x05 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMIT_BW5,         0x05 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW1,       0x08 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW2,       0x07 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW3,       0x05 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW4,       0x05 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_LIMITD1_BW5,       0x05 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW1,          0x03 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW2,          0x03 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW3,          0x03 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW4,          0x03 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_HYST_BW5,          0x03 },
	{ WCD934X_CDC_RATE_EST1_RE_RMAX_DIAG,              0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_RMIN_DIAG,              0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_PH_DET,                 0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_DIAG_CLR,               0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_MB_SW_STATE,            0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_MAST_DIAG_STATE,        0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_RATE_OUT_7_0,           0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_RATE_OUT_15_8,          0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_RATE_OUT_23_16,         0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_RATE_OUT_31_24,         0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_RATE_OUT_39_32,         0x00 },
	{ WCD934X_CDC_RATE_EST1_RE_RATE_OUT_40_43,         0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_CLK_RST_CTL,            0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_CTL,                    0x09 },
	{ WCD934X_CDC_RATE_EST2_RE_PULSE_SUPR_CTL,         0x06 },
	{ WCD934X_CDC_RATE_EST2_RE_TIMER,                  0x01 },
	{ WCD934X_CDC_RATE_EST2_RE_BW_SW,                  0x20 },
	{ WCD934X_CDC_RATE_EST2_RE_THRESH,                 0xa0 },
	{ WCD934X_CDC_RATE_EST2_RE_STATUS,                 0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_CTRL,              0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_TIMER2,            0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW1,        0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW2,        0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW3,        0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW4,        0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_OFFSET_BW5,        0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW1,         0x08 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW2,         0x07 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW3,         0x05 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW4,         0x05 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMIT_BW5,         0x05 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW1,       0x08 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW2,       0x07 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW3,       0x05 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW4,       0x05 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_LIMITD1_BW5,       0x05 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW1,          0x03 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW2,          0x03 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW3,          0x03 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW4,          0x03 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_HYST_BW5,          0x03 },
	{ WCD934X_CDC_RATE_EST2_RE_RMAX_DIAG,              0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_RMIN_DIAG,              0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_PH_DET,                 0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_DIAG_CLR,               0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_MB_SW_STATE,            0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_MAST_DIAG_STATE,        0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_RATE_OUT_7_0,           0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_RATE_OUT_15_8,          0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_RATE_OUT_23_16,         0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_RATE_OUT_31_24,         0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_RATE_OUT_39_32,         0x00 },
	{ WCD934X_CDC_RATE_EST2_RE_RATE_OUT_40_43,         0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_CLK_RST_CTL,            0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_CTL,                    0x09 },
	{ WCD934X_CDC_RATE_EST3_RE_PULSE_SUPR_CTL,         0x06 },
	{ WCD934X_CDC_RATE_EST3_RE_TIMER,                  0x01 },
	{ WCD934X_CDC_RATE_EST3_RE_BW_SW,                  0x20 },
	{ WCD934X_CDC_RATE_EST3_RE_THRESH,                 0xa0 },
	{ WCD934X_CDC_RATE_EST3_RE_STATUS,                 0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_CTRL,              0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_TIMER2,            0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW1,        0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW2,        0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW3,        0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW4,        0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_OFFSET_BW5,        0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW1,         0x08 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW2,         0x07 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW3,         0x05 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW4,         0x05 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMIT_BW5,         0x05 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW1,       0x08 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW2,       0x07 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW3,       0x05 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW4,       0x05 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_LIMITD1_BW5,       0x05 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW1,          0x03 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW2,          0x03 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW3,          0x03 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW4,          0x03 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_HYST_BW5,          0x03 },
	{ WCD934X_CDC_RATE_EST3_RE_RMAX_DIAG,              0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_RMIN_DIAG,              0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_PH_DET,                 0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_DIAG_CLR,               0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_MB_SW_STATE,            0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_MAST_DIAG_STATE,        0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_RATE_OUT_7_0,           0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_RATE_OUT_15_8,          0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_RATE_OUT_23_16,         0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_RATE_OUT_31_24,         0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_RATE_OUT_39_32,         0x00 },
	{ WCD934X_CDC_RATE_EST3_RE_RATE_OUT_40_43,         0x00 },
	{ WCD934X_PAGE15_PAGE_REGISTER,                    0x00 },
	{ WCD934X_SPLINE_SRC0_CLK_RST_CTL_0,               0x20 },
	{ WCD934X_SPLINE_SRC0_STATUS,                      0x00 },
	{ WCD934X_SPLINE_SRC1_CLK_RST_CTL_0,               0x20 },
	{ WCD934X_SPLINE_SRC1_STATUS,                      0x00 },
	{ WCD934X_SPLINE_SRC2_CLK_RST_CTL_0,               0x20 },
	{ WCD934X_SPLINE_SRC2_STATUS,                      0x00 },
	{ WCD934X_SPLINE_SRC3_CLK_RST_CTL_0,               0x20 },
	{ WCD934X_SPLINE_SRC3_STATUS,                      0x00 },
	{ WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG0,               0x11 },
	{ WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG1,               0x20 },
	{ WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG2,               0x00 },
	{ WCD934X_CDC_DEBUG_DSD0_DEBUG_CFG3,               0x08 },
	{ WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG0,               0x11 },
	{ WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG1,               0x20 },
	{ WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG2,               0x00 },
	{ WCD934X_CDC_DEBUG_DSD1_DEBUG_CFG3,               0x08 },
	{ WCD934X_CDC_DEBUG_SPLINE_SRC_DEBUG_CFG0,         0x00 },
	{ WCD934X_CDC_DEBUG_SPLINE_SRC_DEBUG_CFG1,         0x00 },
	{ WCD934X_CDC_DEBUG_RC_RE_ASRC_DEBUG_CFG0,         0x00 },
	{ WCD934X_CDC_DEBUG_ANC0_RC0_FIFO_CTL,             0x4c },
	{ WCD934X_CDC_DEBUG_ANC0_RC1_FIFO_CTL,             0x4c },
	{ WCD934X_CDC_DEBUG_ANC1_RC0_FIFO_CTL,             0x4c },
	{ WCD934X_CDC_DEBUG_ANC1_RC1_FIFO_CTL,             0x4c },
	{ WCD934X_CDC_DEBUG_ANC_RC_RST_DBG_CNTR,           0x00 },
	{ WCD934X_PAGE80_PAGE_REGISTER,                    0x00 },
	{ WCD934X_CODEC_CPR_WR_DATA_0,                     0x00 },
	{ WCD934X_CODEC_CPR_WR_DATA_1,                     0x00 },
	{ WCD934X_CODEC_CPR_WR_DATA_2,                     0x00 },
	{ WCD934X_CODEC_CPR_WR_DATA_3,                     0x00 },
	{ WCD934X_CODEC_CPR_WR_ADDR_0,                     0x00 },
	{ WCD934X_CODEC_CPR_WR_ADDR_1,                     0x00 },
	{ WCD934X_CODEC_CPR_WR_ADDR_2,                     0x00 },
	{ WCD934X_CODEC_CPR_WR_ADDR_3,                     0x00 },
	{ WCD934X_CODEC_CPR_RD_ADDR_0,                     0x00 },
	{ WCD934X_CODEC_CPR_RD_ADDR_1,                     0x00 },
	{ WCD934X_CODEC_CPR_RD_ADDR_2,                     0x00 },
	{ WCD934X_CODEC_CPR_RD_ADDR_3,                     0x00 },
	{ WCD934X_CODEC_CPR_RD_DATA_0,                     0x00 },
	{ WCD934X_CODEC_CPR_RD_DATA_1,                     0x00 },
	{ WCD934X_CODEC_CPR_RD_DATA_2,                     0x00 },
	{ WCD934X_CODEC_CPR_RD_DATA_3,                     0x00 },
	{ WCD934X_CODEC_CPR_ACCESS_CFG,                    0x0f },
	{ WCD934X_CODEC_CPR_ACCESS_STATUS,                 0x03 },
	{ WCD934X_CODEC_CPR_NOM_CX_VDD,                    0xb4 },
	{ WCD934X_CODEC_CPR_SVS_CX_VDD,                    0x5c },
	{ WCD934X_CODEC_CPR_SVS2_CX_VDD,                   0x40 },
	{ WCD934X_CODEC_CPR_NOM_MX_VDD,                    0xb4 },
	{ WCD934X_CODEC_CPR_SVS_MX_VDD,                    0xb4 },
	{ WCD934X_CODEC_CPR_SVS2_MX_VDD,                   0xa0 },
	{ WCD934X_CODEC_CPR_SVS2_MIN_CX_VDD,               0x28 },
	{ WCD934X_CODEC_CPR_MAX_SVS2_STEP,                 0x08 },
	{ WCD934X_CODEC_CPR_CTL,                           0x00 },
	{ WCD934X_CODEC_CPR_SW_MODECHNG_STATUS,            0x00 },
	{ WCD934X_CODEC_CPR_SW_MODECHNG_START,             0x00 },
	{ WCD934X_CODEC_CPR_CPR_STATUS,                    0x00 },
	{ WCD934X_PAGE128_PAGE_REGISTER,                   0x00 },
	{ WCD934X_TLMM_BIST_MODE_PINCFG,                   0x00 },
	{ WCD934X_TLMM_RF_PA_ON_PINCFG,                    0x00 },
	{ WCD934X_TLMM_INTR1_PINCFG,                       0x00 },
	{ WCD934X_TLMM_INTR2_PINCFG,                       0x00 },
	{ WCD934X_TLMM_SWR_DATA_PINCFG,                    0x00 },
	{ WCD934X_TLMM_SWR_CLK_PINCFG,                     0x00 },
	{ WCD934X_TLMM_I2S_2_SCK_PINCFG,                   0x00 },
	{ WCD934X_TLMM_SLIMBUS_DATA1_PINCFG,               0x00 },
	{ WCD934X_TLMM_SLIMBUS_DATA2_PINCFG,               0x00 },
	{ WCD934X_TLMM_SLIMBUS_CLK_PINCFG,                 0x00 },
	{ WCD934X_TLMM_I2C_CLK_PINCFG,                     0x00 },
	{ WCD934X_TLMM_I2C_DATA_PINCFG,                    0x00 },
	{ WCD934X_TLMM_I2S_0_RX_PINCFG,                    0x00 },
	{ WCD934X_TLMM_I2S_0_TX_PINCFG,                    0x00 },
	{ WCD934X_TLMM_I2S_0_SCK_PINCFG,                   0x00 },
	{ WCD934X_TLMM_I2S_0_WS_PINCFG,                    0x00 },
	{ WCD934X_TLMM_I2S_1_RX_PINCFG,                    0x00 },
	{ WCD934X_TLMM_I2S_1_TX_PINCFG,                    0x00 },
	{ WCD934X_TLMM_I2S_1_SCK_PINCFG,                   0x00 },
	{ WCD934X_TLMM_I2S_1_WS_PINCFG,                    0x00 },
	{ WCD934X_TLMM_DMIC1_CLK_PINCFG,                   0x00 },
	{ WCD934X_TLMM_DMIC1_DATA_PINCFG,                  0x00 },
	{ WCD934X_TLMM_DMIC2_CLK_PINCFG,                   0x00 },
	{ WCD934X_TLMM_DMIC2_DATA_PINCFG,                  0x00 },
	{ WCD934X_TLMM_DMIC3_CLK_PINCFG,                   0x00 },
	{ WCD934X_TLMM_DMIC3_DATA_PINCFG,                  0x00 },
	{ WCD934X_TLMM_JTCK_PINCFG,                        0x00 },
	{ WCD934X_TLMM_GPIO1_PINCFG,                       0x00 },
	{ WCD934X_TLMM_GPIO2_PINCFG,                       0x00 },
	{ WCD934X_TLMM_GPIO3_PINCFG,                       0x00 },
	{ WCD934X_TLMM_GPIO4_PINCFG,                       0x00 },
	{ WCD934X_TLMM_SPI_S_CSN_PINCFG,                   0x00 },
	{ WCD934X_TLMM_SPI_S_CLK_PINCFG,                   0x00 },
	{ WCD934X_TLMM_SPI_S_DOUT_PINCFG,                  0x00 },
	{ WCD934X_TLMM_SPI_S_DIN_PINCFG,                   0x00 },
	{ WCD934X_TLMM_BA_N_PINCFG,                        0x00 },
	{ WCD934X_TLMM_GPIO0_PINCFG,                       0x00 },
	{ WCD934X_TLMM_I2S_2_RX_PINCFG,                    0x00 },
	{ WCD934X_TLMM_I2S_2_WS_PINCFG,                    0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_OE_0,                 0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_OE_1,                 0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_OE_2,                 0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_OE_3,                 0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_OE_4,                 0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_DATA_0,               0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_DATA_1,               0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_DATA_2,               0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_DATA_3,               0x00 },
	{ WCD934X_TEST_DEBUG_PIN_CTL_DATA_4,               0x00 },
	{ WCD934X_TEST_DEBUG_PAD_DRVCTL_0,                 0x00 },
	{ WCD934X_TEST_DEBUG_PAD_DRVCTL_1,                 0x00 },
	{ WCD934X_TEST_DEBUG_PIN_STATUS,                   0x00 },
	{ WCD934X_TEST_DEBUG_NPL_DLY_TEST_1,               0x10 },
	{ WCD934X_TEST_DEBUG_NPL_DLY_TEST_2,               0x60 },
	{ WCD934X_TEST_DEBUG_MEM_CTRL,                     0x00 },
	{ WCD934X_TEST_DEBUG_DEBUG_BUS_SEL,                0x00 },
	{ WCD934X_TEST_DEBUG_DEBUG_JTAG,                   0x00 },
	{ WCD934X_TEST_DEBUG_DEBUG_EN_1,                   0x00 },
	{ WCD934X_TEST_DEBUG_DEBUG_EN_2,                   0x00 },
	{ WCD934X_TEST_DEBUG_DEBUG_EN_3,                   0x00 },
	{ WCD934X_TEST_DEBUG_DEBUG_EN_4,                   0x00 },
	{ WCD934X_TEST_DEBUG_DEBUG_EN_5,                   0x00 },
	{ WCD934X_TEST_DEBUG_ANA_DTEST_DIR,                0x00 },
	{ WCD934X_TEST_DEBUG_PAD_INP_DISABLE_0,            0x00 },
	{ WCD934X_TEST_DEBUG_PAD_INP_DISABLE_1,            0x00 },
	{ WCD934X_TEST_DEBUG_PAD_INP_DISABLE_2,            0x00 },
	{ WCD934X_TEST_DEBUG_PAD_INP_DISABLE_3,            0x00 },
	{ WCD934X_TEST_DEBUG_PAD_INP_DISABLE_4,            0x00 },
	{ WCD934X_TEST_DEBUG_SYSMEM_CTRL,                  0x00 },
	{ WCD934X_TEST_DEBUG_SOC_SW_PWR_SEQ_DELAY,         0x00 },
	{ WCD934X_TEST_DEBUG_LVAL_NOM_LOW,                 0x96 },
	{ WCD934X_TEST_DEBUG_LVAL_NOM_HIGH,                0x00 },
	{ WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_LOW,            0x53 },
	{ WCD934X_TEST_DEBUG_LVAL_SVS_SVS2_HIGH,           0x00 },
	{ WCD934X_TEST_DEBUG_SPI_SLAVE_CHAR,               0x00 },
	{ WCD934X_TEST_DEBUG_CODEC_DIAGS,                  0x00 },
};

/*
 * wcd934x_regmap_register_patch: Update register defaults based on version
 * @regmap: handle to wcd9xxx regmap
 * @version: wcd934x version
 *
 * Returns error code in case of failure or 0 for success
 */
int wcd934x_regmap_register_patch(struct regmap *regmap, int revision)
{
	int rc = 0;

	if (!regmap) {
		pr_err("%s: regmap struct is NULL\n", __func__);
		return -EINVAL;
	}

	switch (revision) {
	case TAVIL_VERSION_1_1:
	case TAVIL_VERSION_WCD9340_1_1:
	case TAVIL_VERSION_WCD9341_1_1:
		regcache_cache_only(regmap, true);
		rc = regmap_multi_reg_write(regmap, wcd934x_1_1_defaults,
					    ARRAY_SIZE(wcd934x_1_1_defaults));
		regcache_cache_only(regmap, false);
		break;
	}

	return rc;
}
EXPORT_SYMBOL(wcd934x_regmap_register_patch);

static bool wcd934x_is_readable_register(struct device *dev, unsigned int reg)
{
	u8 pg_num, reg_offset;
	const u8 *reg_tbl = NULL;

	/*
	 * Get the page number from MSB of codec register. If its 0x80, assign
	 * the corresponding page index PAGE_0x80.
	 */
	pg_num = reg >> 0x8;
	if (pg_num == 0x80)
		pg_num = WCD934X_PAGE_0X80;
	else if (pg_num == 0x50)
		pg_num = WCD934X_PAGE_0x50;
	else if (pg_num > 0xF)
		return false;

	reg_tbl = wcd934x_reg[pg_num];
	reg_offset = reg & 0xFF;

	if (reg_tbl && reg_tbl[reg_offset])
		return true;
	else
		return false;
}

static bool wcd934x_is_volatile_register(struct device *dev, unsigned int reg)
{
	u8 pg_num, reg_offset;
	const u8 *reg_tbl = NULL;

	pg_num = reg >> 0x8;
	if (pg_num == 0x80)
		pg_num = WCD934X_PAGE_0X80;
	else if (pg_num == 0x50)
		pg_num = WCD934X_PAGE_0x50;
	else if (pg_num > 0xF)
		return false;

	reg_tbl = wcd934x_reg[pg_num];
	reg_offset = reg & 0xFF;

	if (reg_tbl && reg_tbl[reg_offset] == WCD934X_READ)
		return true;

	/* IIR Coeff registers are not cacheable */
	if ((reg >= WCD934X_CDC_SIDETONE_IIR0_IIR_COEF_B1_CTL) &&
	    (reg <= WCD934X_CDC_SIDETONE_IIR1_IIR_COEF_B2_CTL))
		return true;

	if ((reg >= WCD934X_CDC_ANC0_IIR_COEFF_1_CTL) &&
	    (reg <= WCD934X_CDC_ANC0_FB_GAIN_CTL))
		return true;

	if ((reg >= WCD934X_CDC_ANC1_IIR_COEFF_1_CTL) &&
	    (reg <= WCD934X_CDC_ANC1_FB_GAIN_CTL))
		return true;

	if ((reg >= WCD934X_CODEC_CPR_WR_DATA_0) &&
	    (reg <= WCD934X_CODEC_CPR_RD_DATA_3))
		return true;

	/*
	 * Need to mark volatile for registers that are writable but
	 * only few bits are read-only
	 */
	switch (reg) {
	case WCD934X_CPE_SS_SOC_SW_COLLAPSE_CTL:
	case WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_0:
	case WCD934X_CPE_SS_PWR_SYS_PSTATE_CTL_1:
	case WCD934X_CPE_SS_CPAR_CTL:
	case WCD934X_CPE_SS_STATUS:
	case WCD934X_CODEC_RPM_RST_CTL:
	case WCD934X_SIDO_NEW_VOUT_A_STARTUP:
	case WCD934X_SIDO_NEW_VOUT_D_STARTUP:
	case WCD934X_CODEC_RPM_PWR_CDC_DIG_HM_CTL:
	case WCD934X_ANA_MBHC_MECH:
	case WCD934X_ANA_MBHC_ELECT:
	case WCD934X_ANA_MBHC_ZDET:
	case WCD934X_ANA_MICB2:
	case WCD934X_CODEC_RPM_CLK_MCLK_CFG:
	case WCD934X_CLK_SYS_MCLK_PRG:
	case WCD934X_CHIP_TIER_CTRL_EFUSE_CTL:
	case WCD934X_ANA_BIAS:
	case WCD934X_ANA_BUCK_CTL:
	case WCD934X_ANA_RCO:
	case WCD934X_CODEC_RPM_CLK_GATE:
	case WCD934X_BIAS_VBG_FINE_ADJ:
	case WCD934X_CODEC_CPR_SVS_CX_VDD:
	case WCD934X_CODEC_CPR_SVS2_CX_VDD:
		return true;
	}

	return false;
}

struct regmap_config wcd934x_regmap_config = {
	.reg_bits = 16,
	.val_bits = 8,
	.cache_type = REGCACHE_RBTREE,
	.reg_defaults = wcd934x_defaults,
	.num_reg_defaults = ARRAY_SIZE(wcd934x_defaults),
	.max_register = WCD934X_MAX_REGISTER,
	.volatile_reg = wcd934x_is_volatile_register,
	.readable_reg = wcd934x_is_readable_register,
	.can_multi_write = true,
};
